ADC1175-50CILQ/NOPB National Semiconductor, ADC1175-50CILQ/NOPB Datasheet - Page 4

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ADC1175-50CILQ/NOPB

Manufacturer Part Number
ADC1175-50CILQ/NOPB
Description
IC ADC 8BIT 50MSPS 125MW 24LLP
Manufacturer
National Semiconductor
Datasheet

Specifications of ADC1175-50CILQ/NOPB

Number Of Bits
8
Sampling Rate (per Second)
50M
Data Interface
Parallel
Number Of Converters
1
Power Dissipation (max)
125mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-20°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
24-WFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADC1175-50CILQ
ADC1175-50CILQTR
www.national.com
3 thru 10
(1 thru 8)
(22, 24)
(13, 16)
(18, 19)
11, 13,
(9, 11,
15, 18
20, 21
2, 24
(10)
Pin
No.
12)
12
14
Symbol
D0–D7
DV
DV
AV
AV
CLK
DD
DD
SS
SS
Equivalent Circuit
4
CMOS/TTL compatible digital clock input. V
the falling edge of CLK input.
Conversion data digital Output pins. D0 is the LSB, D7 is
the MSB. Valid data is output just after the rising edge of
the CLK input. These pins are in a high impedance mode
when the PD pin is low.
Positive digital supply pin. Connect to a quiet voltage source
of +5V. AV
be separately bypassed with a 10 µF capacitor and a 0.1
µF ceramic chip capacitor. See Section 4.0 for more
information.
The ground return for the digital supply. AV
should be connected together close to the ADC1175-50.
Positive analog supply pin. Connect to a quiet voltage
source of +5V. AV
source and be separately bypassed with a 10 µF capacitor
and a 0.1 µF ceramic chip capacitor. See Section 4.0 for
more information.
The ground return for the analog supply. AV
should be connected together close to the ADC1175-50
package.
DD
and DV
DD
DD
and DV
Description
should have a common source and
DD
should have a common
IN
SS
SS
is sampled on
and DV
and DV
SS
SS

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