ADC1175-50EVAL National Semiconductor, ADC1175-50EVAL Datasheet
ADC1175-50EVAL
Specifications of ADC1175-50EVAL
Related parts for ADC1175-50EVAL
ADC1175-50EVAL Summary of contents
Page 1
... The top and bottom of the ADC1175's reference ladder is available for connections, en- abling a wide range of input possibilities. The ADC1175 is offered in a TSSOP designed to operate over the commercial temperature range of -20°C to +75°C. Pin Configuration © 2007 National Semiconductor Corporation Features ■ ...
Page 2
... Ordering Information Order Code ADC1175CIJM * ADC1175CIJMX * ADC1175CIMTC ADC1175CIMTCX ADC1175EVAL * * Discontinured in the SOIC (EIAJ) package. The Evaluation Board is also discontinued. Shown for reference only. Block Diagram www.national.com Temperature Description −20°C to +75°C SOIC (EIAJ) −20°C to +75°C SOIC (EIAJ) (tape & reel) − ...
Page 3
... Reference Bottom Bias with internal pull down resistor. Short to V CMOS/TTL compatible Digital input that, when low, enables the digital outputs of the ADC1175. When high, the outputs are in a high impedance state. CMOS/TTL compatible digital clock Input. V the falling edge of CLK input. ...
Page 4
... AV source and be separately bypassed with a 10 µF capacitor and a 0.1 µF ceramic chip capacitor. See Section 3.0 for more information. The ground return for the analog supply. AV should be connected together close to the ADC1175 package. 4 Description and DV should have a common ...
Page 5
... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications Voltage on Any Pin CLK, OE Voltage Digital Output Voltage Input Current (Note 3) Package Input Current (Note 3) Package Dissipation at 25°C ESD Susceptibility (Note 5) ...
Page 6
Symbol Parameter V Reference Top Self Bias Voltage RT Reference Bottom Self Bias V RB Voltage V - RTS Self Bias Voltage Delta V RBS Reference Voltage Delta RT RB Power Supply Characteristics IA Analog Supply Current ...
Page 7
... T JA for maximum power dissipation listed above will be reached only when the ADC1175 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. ...
Page 8
Typical Performance Characteristics INL vs. Temp at f SNR vs. Temp at f THD vs. Temp www.national.com CLK 10009220 CLK 10009222 10009223 8 DNL vs. Temp at f CLK 10009221 SNR vs. Temp at f CLK 10009233 THD vs. Temp ...
Page 9
SINAD/ENOB vs. Temp SINAD and ENOB vs. Clock Duty Cycle SFDR vs. Temp and f IN 10009230 SINAD/ENOB vs. Temp 10009224 SFDR vs. Temp and f 10009225 Differential Gain vs. Temperature 9 10009231 IN 10009229 10009226 www.national.com ...
Page 10
Differential Phase vs. Temperature Specification Definitions ANALOG INPUT BANDWIDTH is a measure of the frequen which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. The test is performed with ...
Page 11
... Timing Diagram FIGURE 1. ADC1175 Timing Diagram 10009212 FIGURE Test Circuit EN DIS 11 10009211 www.national.com ...
Page 12
... OE pin is high. Applications Information 1.0 THE ANALOG INPUT The analog input of the ADC1175 is a switch followed by an integrator. The input capacitance changes with the clock lev- el, appearing when the clock is low, and 11 pF when the clock is high ...
Page 13
FIGURE 3. Simple, Low Component Count, Self -Bias Reference application. Because of resistor tolerances, the reference voltages can vary by as much as 6%. Choose an amplifier that can drive a dynamic capacitance (see text). FIGURE 4. Better defining the ...
Page 14
... An alternative power-saving technique is to power up the and RT ADC1175 with the clock active, then halt the clock in the low state after two or more clock cycles. Stopping the clock in the high state is not recommended as a power-saving technique. 5.0 LAYOUT AND GROUNDING Proper grounding and proper routing of all signals is essential to ensure accurate conversion ...
Page 15
... DYNAMIC PERFORMANCE The ADC1175 is a.c. tested and its dynamic performance is guaranteed. To meet the published specifications, the clock source driving the CLK input must be free of jitter. For best a ...
Page 16
... ADC outputs. The value of these resistors is not critical, as long as they do not cause excessive currents in the outputs of the ADC1175. Low pull-down resis- tor values could result in degraded SNR and SINAD perfor- mance of the ADC1175. Values between 5 kΩ and 100 kΩ should work well. 10009218 10009219 ...
Page 17
... Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Package JM Ordering Number ADC1175CIJM NS Package Number M24D 24-Lead Package TC Ordering Number ADC1175CIMTC NS Package Number MTC24 17 www.national.com ...
Page 18
... National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. ...