MAX11043ATL+ Maxim Integrated Products, MAX11043ATL+ Datasheet - Page 22

• Manufacturer Part Number: MAX11043ATL+
• Description: IC ADC 16BIT W/DAC 40-TQFN-EP
• Manufacturer: Maxim Integrated Products
• Type: ADC, DACr

Specifications of MAX11043ATL+

• Resolution (bits): 16 b
• Sampling Rate (per Second): 9.6M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Number Of Converters: 4
• Conversion Rate: 1600 KSPs
• Resolution: 16 bit
• Interface Type: SPI
• Voltage Reference: 2.5 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Power Dissipation: 2963 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Input Voltage: 3.3 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Reference Register (10h)
Reserved<15:13>: Reserved. Set to 0.
PURGE4:PURGE0<12:8>: Filter purge interval.
Straight binary.
00h = first available sample is presented (default).
1Fh = 31 results are discarded.
Digital filters retain a history of past input data. At
power-up and when changing the signal path, old data
requires purging before new output data is valid.
PURGE4(MSB):PURGE0 determine the number of sam-
ples to discard before a new result is valid. Each time
CONVRUN is taken high, N results are discarded
before EOC asserts low (where N is the decimal equiva-
lent of the binary representation of PURGE4:PURGE0).
Results prior to N+1 are overwritten. EOC asserts for
results N+1, N+2, N+3, etc., as long as CONVRUN
remains high. Taking CONVRUN low and then high
invokes another purge.
Purging of the sinc 5 filter requires five readings if
DECSEL (configuration register 08h, bit 0) = 1 and
three readings if DECSEL = 0. The minimum total purge
interval of the seven cascaded filters is one reading if
not used. If the filters are used, the total latency of the
programmable filters is the sum of the latency caused
by each stage. Set the appropriate delay for filter purg-
ing and settling time.
22
EXTREF
BIT 15
______________________________________________________________________________________
BIT 7
0
EXBUFA
BIT 14
BIT 6
0
EXBUFB
BIT 13
BIT 5
0
PURGE4
EXBUFC
BIT 12
BIT 4
EXTREF<7>: Main reference selection.
1 = external reference applied to REFBP, internal refer-
ence buffer powered down.
0 = internal reference, bypass REFBP with 1µF to
AGND (default).
EXBUF_<6:3>: ADC reference selection for each
channel.
1 = external reference applied to REF_ input, internal
switch open.
0 = using main internal reference, bypass REF_ with
1µF to AGND (default).
EXBUFDAC<2>: Coarse DAC reference selection.
1 = external reference applied to REFDAC, internal ref-
erence buffer powered down.
0 = using main internal reference, bypass REFDAC
with 1µF to AGND (default).
EXBUFDACH<1>: High reference for fine DAC.
1 = external reference applied to REFDACH, internal
reference buffer powered down.
0 = using high output from coarse DAC as reference,
bypass REFDACH with 1µF to AGND (default).
EXBUFDACL<0>: Low reference for fine DAC.
1 = external reference applied to REFDACL, internal
reference buffer powered down.
0 = using low output from coarse DAC as reference,
bypass REFDACL with 1µF to AGND (default).
PURGE3
EXBUFD
BIT 11
BIT 3
EXBUFDAC
PURGE2
BIT 10
BIT 2
EXBUFDACH
PURGE1
BIT 9
BIT 1
EXBUFDACL
PURGE0
BIT 8
BIT 0