MAX1348BETX+T Maxim Integrated Products, MAX1348BETX+T Datasheet - Page 18

• Manufacturer Part Number: MAX1348BETX+T
• Description: IC ADC/DAC 12BIT W/FIFO 36WQFN
• Manufacturer: Maxim Integrated Products
• Type: ADC, DACr

Specifications of MAX1348BETX+T

• Resolution (bits): 12 b
• Sampling Rate (per Second): 225k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-WQFN Exposed Pad, 36-HWQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
In addition to the 12-bit ADC, the MAX1340/MAX1342/
MAX1346/MAX1348 also include four voltage-output,
12-bit, monotonic DACs with less than 4 LSB integral
nonlinearity error and less than 1 LSB differential nonlin-
earity error. Each DAC has a 2µs settling time and ultra-
low glitch energy (4nV
unipolar binary with 1 LSB = V
Figure 1 shows the functional diagram of the MAX1342.
The shift register converts a serial 16-bit word to parallel
data for each input register operating with a clock rate
up to 25MHz. The SPI-compatible digital interface to the
shift register consists of CS, SCLK, DIN, and DOUT.
Serial data at DIN is loaded on the falling edge of SCLK.
Pull CS low to begin a write sequence. Begin a write to
the DAC by writing 0001XXXX as a command byte. The
last 4 bits of the DAC select register are don’t-care bits.
See Table 10. Write another 2 bytes to the DAC inter-
face register following the command byte to select the
appropriate DAC and the data to be written to it. See
Tables 17 and 18.
The four double-buffered DACs include an input and a
DAC register. The input registers are directly connect-
ed to the shift register and hold the result of the most
recent write operation. The four 12-bit DAC registers
hold the current output code for the respective DAC.
Data can be transferred from the input registers to the
DAC registers by pulling LDAC low or by writing the
appropriate DAC command sequence at DIN. See
Table 17. The outputs of the DACs are buffered through
four rail-to-rail op amps.
The MAX1340/MAX1342/MAX1346/MAX1348 DAC out-
put-voltage range is based on the internal reference or
an external reference. Write to the setup register (see
Table 5) to program the reference. If using an external
voltage reference, bypass REF1 with a 0.1µF capacitor
to AGND. The internal reference is 4.096V. When using
an external reference, the voltage range is 0.7V to AV
See Table 2 for various analog outputs from the DAC.
18
______________________________________________________________________________________
•
s). The 12-bit DAC code is
REF
DAC Transfer Function
DAC Digital Interface
/ 4096.
12-Bit DAC
DD
.
The state of the RES_SEL input determines the wake-up
state of the DAC outputs. Connect RES_SEL to AV
AGND upon power-up to be sure the DAC outputs
wake up to a known state. Connect RES_SEL to AGND
to wake up all DAC outputs at 000h. While RES_SEL is
low, the 100kΩ internal resistor pulls the DAC outputs to
AGND and the output buffers are powered down.
Connect RES_SEL to AV
at FFFh. While RES_SEL is high, the 100kΩ pullup
resistor pulls the DAC outputs to V
buffers are powered down.
See Table 18 for a description of the DAC power-up
and power-down modes.
In addition to the internal ADC and DAC, the
MAX1342/MAX1348 also provide four GPIO channels,
GPIOA0, GPIOA1, GPIOC0, GPIOC1. Read and write to
the GPIOs as detailed in Table 1 and Tables 12–16. Also,
see the GPIO Command section. See Figures 11 and 12
for GPIO timing.
Write to the GPIOs by writing a command byte to the
GPIO command register. Write a single data byte to the
MAX1342/MAX1348 following the command byte.
Table 2. DAC Output Code Table
MSB
1111
1000
1000
0111
0000
0000
DAC CONTENTS
1111
0000
0000
0111
0000
0000
1111
0001
0000
0111
0001
0000
LSB
DAC Power-On Wake-Up Modes
DD
to wake up all DAC outputs
+
V
REF
ANALOG OUTPUT
DAC Power-Up Modes
+
+
+
+
V
V
V
V
REF1
⎛
⎜
⎝
REF
REF
REF
2048
4096
REF
and the output
⎛
⎜
⎝
⎛
⎜
⎝
⎛
⎜
⎝
⎛
⎜
⎝
⎞
⎟ =
⎠
0
4095
4096
2047
4096
2049
4096
4096
1
⎛
⎜
⎝
+
⎞
⎟
⎠
GPIOs
⎞
⎟
⎠
⎞
⎟
⎠
⎞
⎟
⎠
V
2
REF
DD
⎞
⎟
⎠
or