MCP4341-502E/ST Microchip Technology, MCP4341-502E/ST Datasheet - Page 36
![IC DGTL POT QUAD 5K 20TSSOP](/photos/29/2/290212/tssop20_sml.jpg)
MCP4341-502E/ST
Manufacturer Part Number
MCP4341-502E/ST
Description
IC DGTL POT QUAD 5K 20TSSOP
Manufacturer
Microchip Technology
Series
WiperLock™r
Datasheet
1.MCP4361-503EML.pdf
(80 pages)
Specifications of MCP4341-502E/ST
Package / Case
20-TSSOP
Taps
129
Resistance (ohms)
5K
Number Of Circuits
4
Temperature Coefficient
150 ppm/°C Typical
Memory Type
Non-Volatile
Interface
SPI Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Resistance In Ohms
5K
Number Of Pots
Quad
Taps Per Pot
129
Resistance
5 KOhms
Wiper Memory
Non Volatile
Buffered Wiper
Buffered
Digital Interface
SPI
Operating Supply Voltage
2.7 V to 5.5 V
Supply Current
450 uA
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCP4341-502E/ST
Manufacturer:
Microchip
Quantity:
329
MCP434X/436X
4.2.2.2
There are two Terminal Control (TCON) Registers.
These are called TCON0 and TCON1. Each register
contains 8 control bits. Four bits for each Wiper.
Register 4-2
while
register.
The state of each resistor network terminal connection
is individually controlled. That is, each terminal
connection (A, B and W) can be individually connected/
disconnected from the resistor network. This allows the
system to minimize the currents through the digital
potentiometer.
DS22233A-page 36
Register 4-3
describes each bit of the TCON0 register,
Terminal Control (TCON) Registers
describes each bit of the TCON1
The value that is written to the specified TCON register
will appear on the appropriate resistor network
terminals when the serial command has completed.
When the WL1 bit is enabled, writes to the TCON0
register bits R1HW, R1A, R1W, and R1B are inhibited.
When the WL0 bit is enabled, writes to the TCON0
register bits R0HW, R0A, R0W, and R0B are inhibited.
When the WL3 bit is enabled, writes to the TCON1
register bits R3HW, R3A, R3W, and R3B are inhibited.
When the WL2 bit is enabled, writes to the TCON1
register bits R2HW, R2A, R2W, and R2B are inhibited.
On a POR/BOR these registers are loaded with
1FFh (9-bits), for all terminals connected. The Host
Controller needs to detect the POR/BOR event and
then update the Volatile TCON register values.
© 2009 Microchip Technology Inc.