AD5165BUJZ100-R2 Analog Devices Inc, AD5165BUJZ100-R2 Datasheet - Page 14

• Manufacturer Part Number: AD5165BUJZ100-R2
• Description: IC DGTL POT 100K LP TSOT23-8
• Manufacturer: Analog Devices Inc

Specifications of AD5165BUJZ100-R2

• Taps: 256
• Resistance (ohms): 100K
• Number Of Circuits: 1
• Temperature Coefficient: 35 ppm/°C Typical
• Memory Type: Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: TSOT-23-8, TSOT-8
• Resistance In Ohms: 100K
• End To End Resistance: 100kohm
• Track Taper: Linear
• No. Of Steps: 256
• Resistance Tolerance: ± 20%
• Supply Voltage Range: 2.7V To 5.5V
• Control Interface: Serial, SPI
• No. Of Pots: Single
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD5165EBZ - BOARD EVALUATION FOR AD5165
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: AD5165BUJZ100-R2; AD5165BUJZ100-R2TR

AD5165
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A to B. Unlike the polarity of V
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V
up to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across terminals A and B divided by the 256
positions of the potentiometer divider. The general equation
defining the output voltage at V
valid input voltage applied to terminals A and B is
A more accurate calculation, which includes the effect of wiper
resistance, V
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors R
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
3-WIRE SERIAL BUS DIGITAL INTERFACE
The AD5165 contains a 3-wire digital interface (SDI, CS, and
CLK). The 8-bit serial word must be loaded MSB first. The
format of the word is shown in Table 5.
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
flip-flop or other suitable means. When CS is high, the clock
loads data into the serial register on each positive clock edge,
as shown in Figure 34.
V
V
W
W
(
(
D
D
)
)
W
=
=
Figure 38. Potentiometer Mode Configuration
, is
256
R
D
WB
R
AB
V
(
D
A
)
V
+
I
V
256
A
+
256
−
R
A
B
WA
D
R
DD
W
AB
W
V
(
D
with respect to ground for any
to GND, which must be
B
WA
)
V
and R
V
B
O
WB
and not the
(3)
(4)
Rev. 0 | Page 14 of 16
The data setup and data hold times in the specifications table
determine the valid timing requirements. The AD5165 uses an
8-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic low.
Extra MSB bits are ignored.
ESD PROTECTION
All digital inputs are protected with a series of input resistors
and parallel Zener ESD structures, shown in Figure 39 and
Figure 40. This applies to the digital input pins SDI, CLK,
and CS.
TERMINAL VOLTAGE OPERATING RANGE
The AD5165 V
conditions for proper 3-terminal digital potentiometer oper-
ation. Supply signals present on terminals A, B, and W that
exceed V
diodes, as shown in Figure 41.
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at terminals A, B, and W (see Figure 41), it is important to
power V
and W; otherwise, the diode is forward biased such that V
powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, V
order of powering V
important as long as they are powered after V
Figure 41. Maximum Terminal Voltages Set by V
DD
DD
DD
, digital inputs, and then V
/GND before applying any voltage to terminals A, B,
or GND are clamped by the internal forward-biased
Figure 40. ESD Protection of Resistor Terminals
DD
Figure 39. ESD Protection of Digital Pins
and GND power supply defines the boundary
A
, V
A, B, W
GND
B
GND
, V
340Ω
W
, and the digital inputs is not
LOGIC
A
, V
B
V
A
W
B
GND
, and V
DD
DD
DD
/GND.
W
and GND
. The relative
DD
is