AD8400AR10 Analog Devices Inc, AD8400AR10 Datasheet - Page 10
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AD8400AR10
Manufacturer Part Number
AD8400AR10
Description
IC DGTL POT 8BIT 10K 1CH 8-SOIC
Manufacturer
Analog Devices Inc
Datasheet
1.AD8400ARZ1.pdf
(32 pages)
Specifications of AD8400AR10
Rohs Status
RoHS non-compliant
Taps
256
Resistance (ohms)
10K
Number Of Circuits
1
Temperature Coefficient
500 ppm/°C Typical
Memory Type
Volatile
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Resistance In Ohms
10K
End To End Resistance
10kohm
Track Taper
Linear
No. Of Steps
256
Resistance Tolerance
± 20%
Supply Voltage Range
2.7V To 5.5V
Control Interface
Serial, SPI
No. Of Pots
Single
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD8400AR10
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD8400AR100
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD8400/AD8402/AD8403
ELECTRICAL CHARACTERISTICS—ALL VERSIONS
V
Table 4.
Parameter
SWITCHING CHARACTERISTICS
1
2
3
4
TIMING DIAGRAMS
V
(DATA OUT)
CLK
Typicals represent average readings at 25°C and V
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal.
The remaining resistor terminals are left open circuit.
See the timing diagram in Figure 3 for location of measured values. All input control voltages are specified with t
timed from a voltage level of 1.6 V. Switching characteristics are measured using V
of 1 V/μs should be maintained.
Propagation delay depends on the value of V
OUT
SDI
DD
CS
(DATA IN)
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay
CS Setup Time
CS High Pulse Width
Reset Pulse Width
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
V
= 3 V ± 10% or 5 V ± 10%, V
DD
0V
V
SDO
CLK
1
0
1
0
1
0
OUT
SDI
CS
V
0V
DD
1
0
1
0
1
0
1
0
A1
A0
Ax OR Dx
A'x OR D'x
t
D7
PD_MIN
Figure 4. Detailed Timing Diagram
t
CSS
D6
Figure 3. Timing Diagram
t
CH
D5
A'x OR D'x
Ax OR Dx
t
DS
D4
t
CL
2, 3
D3
DAC REGISTER LOAD
4
A
t
DH
D2
= V
DD
D1
DD
±1% ERROR BAND
t
, R
CSH
, V
L
DD
, and C
D0
= 5 V.
B
t
PD_MAX
= 0 V, −40°C ≤ T
t
CS1
L
Symbol
t
t
t
t
t
t
t
t
t
(see the Applications section).
t
CH
DS
DH
PD
CSS
CSW
RS
CSH
CS1
S
t
CSW
, t
CL
±1%
Rev. E | Page 10 of 32
A
Conditions
Clock level high or low
R
≤ +125°C, unless otherwise noted.
L
= 1 kΩ to 5 V, C
DD
= 3 V or 5 V. To avoid false clocking, a minimum input logic slew rate
L
≤ 20 pF
V
OUT
RS
V
DD
V
DD
/2
1
0
Figure 5. Reset Timing Diagram
R
= t
F
= 1 ns (10% to 90% of V
±1% ERROR BAND
Min
10
5
5
1
10
10
50
0
10
t
RS
t
S
Typ
1
DD
) and
±1%
Max
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns