AD8400AR10 Analog Devices Inc, AD8400AR10 Datasheet - Page 9
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AD8400AR10
Manufacturer Part Number
AD8400AR10
Description
IC DGTL POT 8BIT 10K 1CH 8-SOIC
Manufacturer
Analog Devices Inc
Datasheet
1.AD8400ARZ1.pdf
(32 pages)
Specifications of AD8400AR10
Rohs Status
RoHS non-compliant
Taps
256
Resistance (ohms)
10K
Number Of Circuits
1
Temperature Coefficient
500 ppm/°C Typical
Memory Type
Volatile
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Resistance In Ohms
10K
End To End Resistance
10kohm
Track Taper
Linear
No. Of Steps
256
Resistance Tolerance
± 20%
Supply Voltage Range
2.7V To 5.5V
Control Interface
Serial, SPI
No. Of Pots
Single
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD8400AR10
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD8400AR100
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Parameter
DYNAMIC CHARACTERISTICS
1
2
3
4
5
6
7
8
9
10
11
Typicals represent average readings at 25°C and V
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. See the test circuit in Figure 38. I
I
V
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37.
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal.
The remaining resistor terminals are left open circuit.
Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See Figure 28 for a plot of I
P
W
All dynamic characteristics use V
Measured at a V
AB
DISS
Bandwidth −3 dB
Total Harmonic Distortion
V
Resistor Noise Voltage
Crosstalk
= 2.5 mA for V
W
= V
is calculated from (I
Settling Time
DD
, wiper (V
11
DD
W
W
pin where an adjacent V
= 5 V for 1 kΩ version.
) = no connect.
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
DD
6, 10
= 5 V.
W
pin is making a full-scale voltage change.
DD
= 5 V.
Symbol
BW_1 K
THD
t
e
C
S
NWB
T
W
Conditions
R = 1 kΩ
V
V
R
V
A
A
WB
A
= 1 V rms + 2 V dc, V
= V
= V
Rev. E | Page 9 of 32
= 500 Ω, f = 1 kHz, RS = 0
DD
DD
, V
, V
B
B
= 0 V, ±1% error band
= 0 V
B
= 2 V dc, f = 1 kHz
AD8400/AD8402/AD8403
Min
W
A
= 500 μA for V
= V
DD
Typ
5,000
0.015
0.5
3
−65
and V
1
DD
B
= 0 V.
DD
vs. logic voltage.
Max
= 3 V and
Unit
kHz
%
μs
nV/√Hz
dB