ISL22426UFV14Z-TK Intersil, ISL22426UFV14Z-TK Datasheet - Page 12

• Manufacturer Part Number: ISL22426UFV14Z-TK
• Description: IC POT DGTL 128TP LN LP 14-TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL22426UFV14Z-TK

• Taps: 128
• Resistance (ohms): 50K
• Number Of Circuits: 2
• Temperature Coefficient: 80 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

controlled by the host or master. The ISL22426 operates
only as a slave device.
All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
The first byte sent to the ISL22426 from the SPI host is the
Identification Byte. A valid Identification Byte contains 0101
as the four MSBs, with the following four bits set to 0.
The next byte sent to the ISL22426 contains the instruction
and register pointer information. The four MSBs are the
instruction and four LSBs are register address (see Table 5).
There are only two valid instruction sets:
1011(binary) - is a Read operation
1100(binary) - is a Write operation
Write Operation
A Write operation to the ISL22426 is a three-byte operation.
It first requires the CS transition from HIGH to LOW, then a
valid Identification Byte, then a valid instruction byte
following by Data Byte is sent to SDI pin. The host
terminates the write operation by pulling the CS pin from
LOW to HIGH. For a write to addresses 0000b or 0001b, the
MSB at address 8 (ACR[7]) determines if the Data Byte is to
(MSB)
I3
0
7
SCK
SDO
SCK
SDI
SDI
CS
CS
TABLE 4. IDENTIFICATION BYTE FORMAT
TABLE 5. IDENTIFICATION BYTE FORMAT
I2
1
6
0
0
I1
0
5
1
1
0
0
I0
1
4
1
1
12
0
0
R3
0
3
0
0
0
0
R2
0
2
0
0
FIGURE 16. THREE BYTE WRITE SEQUENCE
FIGURE 17. THREE BYTE READ SEQUENCE
0
0
R1
0
1
I3
I3
(LSB)
I2
I2
R0
0
0
ISL22426
I1
I1
I0
I0
R3 R2
R3 R2
be written to volatile or both volatile and non-volatile
registers. Refer to “Memory Description” on page 11 and
Figure 16.
Device can receive more than one byte of data by auto
incrementing the address after each received byte. Note
after reaching the address 0110b, the internal pointer “rolls
over” to address 0000b.
The internal non-volatile write cycle starts after rising edge of
CS and takes up to 20ms. Thus, non-volatile registers must
be written individually.
Read Operation
A read operation to the ISL22426 is a three-byte operation. It
requires first, the CS transition from HIGH to LOW, then a
valid Identification Byte, then a valid instruction byte
following by “dummy” Data Byte is sent to SDI pin. The SPI
host reads the data from SDO pin on falling edge of SCK.
The host terminates the read operation by pulling the CS pin
from LOW to HIGH (see Figure 17).
The ISL22426 will provide the Data Bytes to the SDO pin as
long as SCK is provided by the host from the registers
indicated by an internal pointer. This pointer initial value is
determined by the register address in the Read operation
instruction, and increments by one during transmission of
each Data Byte. After reaching the memory location 0110b,
the pointer “rolls over” to 0000b, and the device continues to
output the data for each received SCK clock.
In order to read back the non-volatile IVR, it is recommended
that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.
R1 R0
R1 R0
0
0
D6 D5 D4
D6 D5 D4
DON’T CARE
D3 D2
D3 D2
D1 D0
D1 D0
September 8, 2009
FN6180.2