X9269TV24IZ-2.7T1 Intersil, X9269TV24IZ-2.7T1 Datasheet - Page 8

• Manufacturer Part Number: X9269TV24IZ-2.7T1
• Description: IC POT XDCP DUAL 50K OHM 24-SOIC
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X9269TV24IZ-2.7T1

• Taps: 256
• Resistance (ohms): 100K
• Number Of Circuits: 2
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 100K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Acknowledge Polling
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9269
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9269 is still busy with the write operation no ACK
will be returned. If the X9269 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.
FLOW 1: ACK Polling Sequence
Command Completed
EnterACK Polling
Nonvolatile Write
Issue Slave
Operation?
Instruction
Returned?
START
Address
Proceed
Further
Issue
Issue
ACK
Yes
Yes
No
No
8
Issue STOP
Issue STOP
Proceed
X9269
INSTRUCTION AND REGISTER DESCRIPTION
Instructions
D
The first byte sent to the X9269 from the host is called
the Identification Byte. The most significant four bits of
the slave address are a device type identifier. The
ID[3:0] bits is the device id for the X9269; this is fixed
as 0101[B] (refer to Table 1).
The A[3:0] bits in the ID byte is the internal slave
address. The physical device address is defined by
the state of the A3-A0 input pins. The slave address
is externally specified by the user. The X9269
compares the serial data stream with the address
input state; a successful compare of both address
bits is required for the X9269 to successfully continue
the command sequence. Only the device which slave
address matches the incoming device address sent
by the master executes the instruction. The A3 - A0
inputs can be actively driven by CMOS input signals
or tied to V
I
The next byte sent to the X9269 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode I [3:0]. The RB and RA bits point to one of the
four Data Registers of each associated XDCP. The
least significant bit points to one of two Wiper Counter
Registers or Pots. The format is shown in Table 2.
Register Selection
NSTRUCTION
EVICE
Register Selected
A
DDRESSING
CC
DR0
DR1
DR2
DR3
or V
B
YTE
SS
(I)
: I
.
DENTIFICATION
RB
0
0
1
1
B
YTE
(ID
April 17, 2007
RA
AND
0
1
0
1
FN8173.4
A)