CAT5221WI-50-T1 ON Semiconductor, CAT5221WI-50-T1 Datasheet - Page 11
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CAT5221WI-50-T1
Manufacturer Part Number
CAT5221WI-50-T1
Description
IC POT DPP 50K 64TAP 20SOIC
Manufacturer
ON Semiconductor
Datasheet
1.CAT5221YI-25-T2.pdf
(16 pages)
Specifications of CAT5221WI-50-T1
Taps
64
Resistance (ohms)
50K
Number Of Circuits
2
Temperature Coefficient
300 ppm/°C Typical
Memory Type
Non-Volatile
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.5 V ~ 6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Resistance In Ohms
50K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
illustrated in Figure 11. These three−byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper. The
response of the wiper to this action will be delayed by t
A transfer from the WCR (current wiper position), to a Data
Register is a write to non−volatile memory and takes a
maximum of t
between one of the four potentiometers and one of its
associated registers; or the transfer can occur between all
potentiometers and one associated register.
complete, as illustrated in Figure 10. These instructions
transfer data between the host/processor and the CAT5221;
either between the host and one of the data registers or
directly between the host and the Wiper Control Register.
These instructions are:
The basic sequence of the three byte instructions is
Four instructions require a two−byte sequence to
SDA
♦
♦
SDA
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
XFR Data Register to Wiper Control Register −
XFR Wiper Control Register to Data Register −
S
T
A
R
T
ID3 ID2 ID1 ID0
S
T
A
R
T
0
Device ID
ID3 ID2
WR
0
1
Device ID
SDA
to complete. The transfer can occur
1
0
ID1 ID0
0
1
S
T
A
R
T
A3
1
ID3
0
Address
A2 A1 A0
Internal
Device ID
A3
Figure 12. Increment/Decrement
ID2
1
Address
Internal
A2 A1 A0
ID1 ID0
0
Figure 11. Three−Byte Instruction Sequence
Figure 10. Two−Byte Instruction Sequence
1
A
C
K
A3
I3
Address
A2
Internal
A
C
K
Instruction
Opcode
I2
I3
http://onsemi.com
A1
WRL
Instruction
Opcode
I1 I0
A0
I2
.
A
C
K
I1 I0
11
Pot/WCR
Address
0 P0
I3
Increment/Decrement Command
and 12). The Increment/Decrement command is different
from the other commands. Once the command is issued and
the CAT5221 has responded with an acknowledge, the
master can clock the selected wiper up and/or down in one
segment steps; thereby providing a fine tuning capability to
the host. For each SCL clock pulse (t
HIGH, the selected wiper will move one resistor segment
towards the R
pulse while SDA is LOW, the selected wiper will move one
resistor segment towards the R
Instruction
Opcode
Pot/WCR
The final command is Increment/Decrement (Figures 6
See Instructions format for more detail.
Address
I2
Instruction
♦
♦
0
R1 R0
Register − This transfers the contents of all specified
Data Registers to the associated Wiper Control
Registers.
Register − This transfers the contents of all Wiper
Control Registers to the specified associated Data
Registers.
Global XFR Data Register to Wiper Control
Global XFR Wiper Counter Register to Data
Data
Register
Address
P0
I1 I0
R1
Register
Address
Pot/WCR
C
Address
A
K
Data
0 P0
H
R0
Sequence
D7 D6 D5 D4 D3 D2 D1 D0
terminal. Similarly, for each SCL clock
A
C
K
Register
Address
R1 R0 A
Data Register D[7:0]
N
C
1
I
WCR[7:0]
N
C
2
I
C
K
or
L
terminal.
O
S
T
P
N
C
n
I
HIGH
D
C
E
1
) while SDA is
D
C
E
C
n
A
K
O
S
T
P
S
O
P
T