CAT5221WI-50-T1 ON Semiconductor, CAT5221WI-50-T1 Datasheet - Page 9

• Manufacturer Part Number: CAT5221WI-50-T1
• Description: IC POT DPP 50K 64TAP 20SOIC
• Manufacturer: ON Semiconductor

Specifications of CAT5221WI-50-T1

• Taps: 64
• Resistance (ohms): 50K
• Number Of Circuits: 2
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Instructions and Register Description
INSTRUCTIONS
Slave Address Byte
processor is called the Slave/DPP Address Byte. The most
significant four bits of the slave address are a device type
identifier. These bits for the CAT5221 are fixed at 0101[B]
(refer to Figure 8).
and must match the physical device address which is defined
by the state of the A3 − A0 input pins for the CAT5221 to
successfully continue the command sequence. Only the
device which slave address matches the incoming device
address sent by the master executes the instruction. The A3
− A0 inputs can be actively driven by CMOS input signals
or tied to V
The first byte sent to the CAT5221 from the master/
The next four bits, A3 − A0, are the internal slave address
CC
or V
(MSB)
(MSB)
ID3
I3
SS
0
.
ID2
I2
1
Device Type
Instruction
Identifier
Opcode
ID1
Figure 8. Identification Byte Format
I1
Figure 9. Instruction Byte Format
0
http://onsemi.com
ID0
I0
1
9
Instruction Byte
instruction and register pointer information. The four most
significant bits used provide the instruction opcode I [3:0].
The P0 bit points to one of the Wiper Control Registers. The
least two significant bits, R1 and R0, point to one of the four
data registers of each associated potentiometer. The format
is shown in Figure 9.
Table 11. DATA REGISTER SELECTION
WCR/Pot Selection
A3
0
The next byte sent to the CAT5221 contains the
Data Register Selected
A2
P0
DR0
DR1
DR2
DR3
Slave Address
R1
A1
Data Register
Selection
(LSB)
(LSB)
R0
A0
R1
0
0
1
1
R0
0
1
0
1