AD5273BRJ50-R2 Analog Devices Inc, AD5273BRJ50-R2 Datasheet - Page 13

• Manufacturer Part Number: AD5273BRJ50-R2
• Description: IC DGTL POT 50K 64POS SOT23-8
• Manufacturer: Analog Devices Inc

Specifications of AD5273BRJ50-R2

• Rohs Status: RoHS non-compliant
• Taps: 64
• Resistance (ohms): 50K
• Number Of Circuits: 1
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-8
• Resistance In Ohms: 50K
• For Use With: AD5273EVAL - BOARD EVAL FOR AD5273
• Other names: AD5273BRJ50-R2; AD5273BRJ50-R2TR

THEORY OF OPERATION
The AD5273 is a one-time programmable (OTP), set-and-forget,
6-bit digital potentiometer. The AD5273 allows unlimited 6-bit
adjustments prior to the OTP. OTP technology is a proven cost-
effective alternative over EEMEM in one-time memory program-
ming applications. The AD5273 employs fuse link technology to
achieve the memory retention of the resistance setting function.
It comprises six data fuses, which control the address decoder for
programming the RDAC, one user mode test fuse for checking setup
error, and one programming lock fuse for disabling any further
programming once the data fuses are programmed correctly.
ONE-TIME PROGRAMMING
Prior to OTP activation, the AD5273 presets to midscale during
power-on. After the wiper is set to the desired position, the resis-
tance can be permanently set by programming the T bit and the
one-time V
Figure 31). To blow the fuses to achieve a given nonvolatile setting,
the fuse link technology of the AD5273 requires a V
SDA Bit Definitions and Descriptions
S = start condition.
P = stop condition.
A = acknowledge.
X = don’t care.
T = OTP programming bit. Logic 1 programs wiper position
permanently.
D5, D4, D3, D2, D1, D0 = data bits.
S
0
DD_OTP
1
SLAVE ADDRESS BYTE
to high and by coding the part properly (see
0
1
S
SDA
SCL
1
0
0
1
AD0
SLAVE ADDRESS BYTE
0
0
CONTROL BLOCK
PROGRAM/TEST
I
2
1
C INTERFACE
ONE-TIME
A
COMPARATOR
1
T
Figure 30. Detailed Functional Block Diagram
0
DD_OTP
Figure 31. SDA Write Mode Bit Format
Figure 32. SDA Read Mode Bit Format
X
AD0
INSTRUCTION BYTE
X
from
Rev. H | Page 13 of 24
1
X
A
FUSES
REG.
DAC
X
EN
E1
X
5 V to 5.5 V for the 1 kΩ (DD8) and 10 kΩ (DD9) options, or
from 4.75 V to 5.25 V for the 50 kΩ (DYG) and 100 kΩ (DYH)
options. During operation, however, V
Therefore, a system supply that is lower than V
external supply for OTP. The user is allowed only one attempt
to blow the fuses. If the user fails to blow the fuses on the first
attempt, the fuse structure may change such that they can never
be blown, regardless of the energy applied during subsequent
events. For details, see the Power Supply Considerations section.
The device control circuit has two validation bits, E1 and E0,
that can be read back in the read mode to check the program-
ming status, as shown in Figure 32. Users should always read
back the validation bits to ensure that the fuses are properly
blown. After the fuses have been blown, all fuse latches are
enabled upon subsequent power-on; therefore, the output
corresponds to the stored setting. Figure 30 shows a detailed
functional block diagram.
E1, E0 = OTP validation bits.
AD0 = I
AD5273s to be addressed.
E0
X
MUX
D5
0, 0 = ready to program.
0, 1 = test fuse not blown successfully. (For factory setup
checking purpose only. Users should not see these
combinations.)
1, 0 = fatal error. Do not retry. Discard the unit.
1, 1 = programmed successfully. No further adjustments
possible.
X
DATA BYTE
FUSE
REG.
2
D4
C device address bit. Allows maximum of two
A
D3
DECODER
X
D2
X
D1
D5
D0
DATA BYTE
D4
A
D3
B
A
W
P
D2
DD
can be 2.7 V to 5.5 V.
D1
DD_OTP
D0
requires an
AD5273
A
P