X9250TS24I-2.7T2 Intersil, X9250TS24I-2.7T2 Datasheet - Page 5
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X9250TS24I-2.7T2
Manufacturer Part Number
X9250TS24I-2.7T2
Description
IC XDCP QUAD 256-TAP 100K 24SOIC
Manufacturer
Intersil
Series
XDCP™r
Datasheet
1.X9250US24.pdf
(20 pages)
Specifications of X9250TS24I-2.7T2
Taps
256
Resistance (ohms)
100K
Number Of Circuits
4
Temperature Coefficient
300 ppm/°C Typical
Memory Type
Non-Volatile
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-SOIC (7.5mm Width)
Resistance In Ohms
100K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Figure 1. Detailed Potentiometer Block Diagram
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a write in process bit
(WIP). The WIP bit is read with a read status
command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9250 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9250 this is fixed as 0101[B] (refer to Figure 2).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A
pins. The X9250 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9250 to successfully
continue the command sequence. The A
can be actively driven by CMOS input signals or tied to
V
The remaining two bits in the slave byte must be set to 0.
CC
If WCR = 00[H] then V
If WCR = FF[H] then V
(One of Four Arrays)
or V
Serial Data Path
From Interface
SS
Circuitry
.
W
W
/R
/R
W
W
5
= V
= V
L
Register 0
Register 2
H
/R
/R
L
H
0
0
8
- A
- A
1
1
inputs
Register 1
Register 3
input
Modified SCK
X9250
UP/DN
8
Figure 2. Identification Byte Format
Instruction Byte
The next byte sent to the X9250 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the four pots and, when applicable,
they point to one of four associated registers. The
format is shown below in Figure 3.
Figure 3. Instruction Byte Format
Parallel
Bus
Input
UP/DN
CLK
Serial
Bus
Input
Register
Counter
Inc/Dec
0
I3
(WCR)
Logic
Wiper
Device Type
Instructions
Identifier
1
I2
0
I1
C
D
o
u
n
e
e
c
o
d
e
t
r
1
I0
0
Register
R1
Select
0
R0
Device Address
Pot Select
A1
P1
V
V
V
H
L
W
A0
P0
August 29, 2006
/R
/R
/R
L
H
W
FN8165.3