AD9704BCPZ Analog Devices Inc, AD9704BCPZ Datasheet
AD9704BCPZ
Specifications of AD9704BCPZ
Available stocks
Related parts for AD9704BCPZ
AD9704BCPZ Summary of contents
Page 1
FEATURES 175 MSPS update rate Low power member of pin-compatible TxDAC product family Low power dissipation MSPS, 1 175 MSPS, 3.3 V Wide supply voltage: 1 3.6 V SFDR to ...
Page 2
AD9704/AD9705/AD9706/AD9707 TABLE OF CONTENTS Features .............................................................................................. 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 DC Specifications (3.3 V)............................................................ 4 Dynamic Specifications (3.3 V).................................................. 5 Digital Specifications (3.3 V) ...
Page 3
GENERAL DESCRIPTION The AD9704/AD9705/AD9706/AD9707 are the fourth-generation family in the TxDAC series of high performance, CMOS digital-to- analog converters (DACs). This pin-compatible, 8-/10-/12-/14-bit resolution family is optimized for low power operation, while maintaining excellent dynamic performance. The AD9704/ AD9705/AD9706/AD9707 family ...
Page 4
AD9704/AD9705/AD9706/AD9707 SPECIFICATIONS DC SPECIFICATIONS (3 AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3 MIN MAX Table 1. Parameter Min RESOLUTION ACCURACY Integral Nonlinearity (INL) Precalibration Integral Nonlinearity ...
Page 5
Parameter Min Supply Current Clock Power- 5 Down Mode (I ) DVDD Supply Current Clock Power- 5 Down Mode (I ) CLKVDD Power Supply Rejection Ratio −0.2 6 (AVDD) OPERATING RANGE −40 1 Measured at IOUTA, driving a virtual ground, ...
Page 6
AD9704/AD9705/AD9706/AD9707 DIGITAL SPECIFICATIONS (3 AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3 MIN MAX Table 3. Parameter Min DIGITAL INPUTS 1 Logic 1 Voltage 2.1 Logic 0 Voltage Logic 1 ...
Page 7
DC SPECIFICATIONS (1 AVDD = 1.8 V, DVDD = 1.8 V, CLKVDD = 1 MIN MAX Table 4. AD9707 Parameter Min RESOLUTION ACCURACY Integral Nonlinearity (INL) Precalibration Differential Nonlinearity (DNL) ...
Page 8
AD9704/AD9705/AD9706/AD9707 AD9707 Parameter Min Supply Current Clock Power- 4 Down Mode (I ) DVDD Supply Current Clock 4 Power-Down Mode (I ) CLKVDD Power Supply Rejection Ratio −1 5 (AVDD) OPERATING RANGE −40 1 Measured at IOUTA, driving a virtual ...
Page 9
DIGITAL SPECIFICATIONS (1 AVDD = 1.8 V, DVDD = 1.8 V, CLKVDD = 1 MIN MAX Table 6. Parameter Min DIGITAL INPUTS 1 Logic 1 Voltage 1.2 Logic 0 Voltage Logic 1 Current ...
Page 10
AD9704/AD9705/AD9706/AD9707 ABSOLUTE MAXIMUM RATINGS Table 7. With Parameter Respect to AVDD ACOM DVDD DCOM CLKVDD CLKCOM ACOM DCOM ACOM CLKCOM DCOM CLKCOM AVDD DVDD AVDD CLKVDD DVDD CLKVDD SLEEP DCOM Digital Inputs, MODE DCOM IOUTA, IOUTB ACOM REFIO, FS ADJ, ...
Page 11
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AD9707 Table 9. AD9707 Pin Function Descriptions Pin No. Mnemonic Description 27 DB13 (MSB) Most Significant Data Bit (MSB 32, 1, DB12 to DB1 Data Bit 12 to Data Bit ...
Page 12
AD9704/AD9705/AD9706/AD9707 AD9706 Table 10. AD9706 Pin Function Descriptions Pin No. Mnemonic Description 27 DB11 (MSB) Most Significant Data Bit (MSB 32, DB10 to DB1 Data Bit 10 to Data Bit DB0 ...
Page 13
AD9705 Table 11. AD9705 Pin Function Descriptions Pin No. Mnemonic Description 27 DB9 (MSB) Most Significant Data Bit (MSB 32, DB8 to DB1 Data Bit 8 to Data Bit DB0 (LSB) Least Significant ...
Page 14
AD9704/AD9705/AD9706/AD9707 AD9704 Table 12. AD9704 Pin Function Descriptions Pin No. Mnemonic Description 27 DB7 (MSB) Most Significant Data Bit (MSB 32, 1 DB6 to DB1 Data Bit 6 to Data Bit 1. 2 DB0 (LSB) Least Significant Data ...
Page 15
TYPICAL PERFORMANCE CHARACTERISTICS AD9707 VDD = 3 mA, unless otherwise noted. OUTFS 10MSPS CLOCK 65MSPS CLOCK 175MSPS 70 CLOCK 125MSPS 60 CLOCK ...
Page 16
AD9704/AD9705/AD9706/AD9707 OTCM = OTCM = 1. (MHz) OUT Figure 13. SFDR vs. f and OTCM @ 175 MSPS OUT 95 f ...
Page 17
CODE Figure 19. Typical Uncalibrated INL 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 0 5000 10000 CODE Figure 20. Typical Uncalibrated DNL 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 ...
Page 18
AD9704/AD9705/AD9706/AD9707 –10 f – –30 SFDR = 74dBc AMPLITUDE = 0dBFS –40 –50 –60 –70 –80 –90 –100 –110 FREQUENCY (MHz) Figure 25. Dual-Tone SFDR = 78MSPS CLOCK = 15.0MHz OUT1 = 15.4MHz ...
Page 19
VDD = 1 mA, unless otherwise noted. OUTFS 10MSPS CLOCK 65MSPS CLOCK 80MSPS CLOCK (MHz) OUT ...
Page 20
AD9704/AD9705/AD9706/AD9707 –115 –120 –125 –130 f = 65MSPS, CLOCK I = 1mA OUTFS –135 –140 –145 f = 65MSPS, CLOCK I = 2mA –150 OUTFS –155 –160 (dBFS) OUT Figure 33. NSD vs. f ...
Page 21
CODE Figure 39. Typical Uncalibrated DNL –40° +85°C +25° (MHz) OUT ...
Page 22
AD9704/AD9705/AD9706/AD9707 AD9704, AD9705, AND AD9706 VDD = 3 mA, unless otherwise noted. OUTFS –115 AD9704 –120 –125 –130 AD9705 –135 –140 –145 AD9706 –150 AD9707 –155 –160 (MHz) OUT ...
Page 23
CODE Figure 50. AD9706 Typical Uncalibrated DNL – 78MSPS CLOCK – 15.0MHz OUT SFDR = 67dBc –30 AMPLITUDE = 0dBFS –40 –50 –60 –70 –80 –90 ...
Page 24
AD9704/AD9705/AD9706/AD9707 –10 f – –30 SFDR = 77dBc AMPLITUDE = 0dBFS –40 –50 –60 –70 –80 –90 –100 –110 FREQUENCY (MHz) Figure 56. AD9706 Dual-Tone SFDR = 78MSPS CLOCK = 15.0MHz OUT1 = ...
Page 25
VDD = 1 mA, unless otherwise noted. OUTFS –115 –120 AD9704 –125 –130 AD9705 –135 –140 –145 AD9706 AD9707 –150 –155 –160 (MHz) OUT Figure 57. AD9704, AD9705, AD9706, ...
Page 26
AD9704/AD9705/AD9706/AD9707 0.1 0 –0.1 –0.2 –0.3 –0.4 0 1000 2000 CODE Figure 63. AD9706 Typical Uncalibrated DNL –10 f –20 f SFDR = 67dBc –30 AMPLITUDE = 0dBFS –40 –50 –60 –70 –80 –90 –100 –110 ...
Page 27
CLOCK – 15.0MHz OUT1 f = 15.4MHz OUT2 –30 SFDR = 73dBc AMPLITUDE = 0dBFS –40 –50 –60 –70 –80 –90 –100 –110 FREQUENCY (MHz) Figure 69. AD9706 ...
Page 28
AD9704/AD9705/AD9706/AD9707 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (DNL) DNL is ...
Page 29
THEORY OF OPERATION Figure 71 shows a simplified block diagram of the AD9707. The AD9704/AD9705/AD9706/AD9707 consist of a DAC, digital control logic, and full-scale output current control. The DAC contains a PMOS current source array capable of providing a nominal ...
Page 30
AD9704/AD9705/AD9706/AD9707 A logic high on Pin 17 (PIN/SPI/RESET), followed by a logic low, resets the SPI port timing to the initial state of the instruction cycle. This is true regardless of the present state of the internal registers or the ...
Page 31
INSTRUCTION CYCLE DATA TRANSFER CYCLE CSB SCLK R SDIO N Figure 72. Serial Register Interface Timing, MSB First Write INSTRUCTION CYCLE DATA TRANSFER CYCLE CSB SCLK R ...
Page 32
AD9704/AD9705/AD9706/AD9707 SPI REGISTER DESCRIPTIONS Table 16. SPI CTL—Register 0x00 Mnemonic Bit No. Direction (I/O) SDIODIR 7 I DATADIR 6 I SWRST 5 I LNGINS 4 I PDN 3 I SLEEP 2 I CLKOFF 1 I EXREF 0 I Table 17. ...
Page 33
Table 20. MEMRDWR—Register 0x0F Mnemonic Bit No. Direction (I/O) CALSTAT 7 O CALEN 6 I SMEMWR 3 I SMEMRD 2 I UNCAL 0 I Table 21. MEMADDR—Register 0x10 Mnemonic Bit No. Direction (I/O) MEMADDR[5:0] [5:0] I/O Table 22. MEMDATA—Register 0x11 ...
Page 34
AD9704/AD9705/AD9706/AD9707 REFERENCE OPERATION The AD9704/AD9705/AD9706/AD9707 contain an internal 1.0 V band gap reference. The internal reference can be disabled by writing a Logic 1 to Register 0x00, Bit 0 (EXREF) in the SPI. To use the internal reference, decouple the ...
Page 35
Equation 7 and Equation 8 highlight some of the advantages of operating the AD9704/AD9705/AD9706/AD9707 differentially. First, the differential operation helps cancel common-mode error sources associated with IOUTA and IOUTB, such as noise, distortion, and dc offsets. Second, the differential code ...
Page 36
AD9704/AD9705/AD9706/AD9707 DIGITAL INPUT Figure 79. Equivalent Digital Input The digital interface is implemented using an edge-triggered master/slave latch. The DAC output updates on the rising edge of the clock and is designed to support a clock rate as high as ...
Page 37
I (mA) OUTFS Figure 81 AVDD = 3.3 V AVDD OUTFS 1.00 1.25 1.50 ...
Page 38
AD9704/AD9705/AD9706/AD9707 Sleep and Power-Down Operation (Pin Mode) The AD9704/AD9705/AD9706/AD9707 have a sleep mode that turns off the output current and reduces the total power consumed by the device. This mode is activated by applying a Logic 1 to the SLEEP/CSB ...
Page 39
The calibration clock frequency is equal to the DAC clock divided by the division factor chosen by the DIVSEL value. The frequency of the calibration clock must be set to under 10 MHz for reliable calibrations. Best results are obtained ...
Page 40
AD9704/AD9705/AD9706/AD9707 APPLICATIONS OUTPUT CONFIGURATIONS The following sections illustrate some typical output configurations for the AD9704/AD9705/AD9706/AD9707. Unless otherwise noted assumed that I nominal 2 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A ...
Page 41
DIFFERENTIAL BUFFERED OUTPUT USING AN OP AMP A dual op amp (see the circuit shown in Figure 91) can be used in a differential version of the single-ended buffer shown in Figure 90. The same R-C network is used to ...
Page 42
AD9704/AD9705/AD9706/AD9707 EVALUATION BOARD GENERAL DESCRIPTION The TxDAC family evaluation boards allow for easy setup and testing of any TxDAC products. Careful attention to layout and circuit design, combined with a prototyping area, allows the user to evaluate the AD9704/AD9705/AD9706/AD9707 easily ...
Page 43
EVALUATION BOARD SCHEMATICS ...
Page 44
AD9704/AD9705/AD9706/AD9707 3 RC060 3 RC060 3 RC060 3 RC060 Figure 93. Output Signal Conditioning Rev Page 05926-052 3 RC060 RC080 5 JP9 ERA6YEB323V,ERA6Y RC080 5 JP8 ERA6YEB323V,ERA6Y RC080 5 JP7 ERA6YEB323V,ERA6Y 3 RC060 R7 ...
Page 45
RC0603 JP20 JP23 CC0603 JP30 JP21 Figure 94. Clock Rev Page AD9704/AD9705/AD9706/AD9707 05926-053 RC0603 CC0603 JP16 ...
Page 46
AD9704/AD9705/AD9706/AD9707 3 RC060 JP5 3 RC060 JP4 JP1 3 RC060 Figure 95. SPI Rev Page 05926-054 ...
Page 47
RC0603 RC0603 CC0603 CC0603 Figure 96. Power Supplies Rev Page AD9704/AD9705/AD9706/AD9707 05926-077 RC0603 RC0603 CC0603 CC0603 ...
Page 48
AD9704/AD9705/AD9706/AD9707 EVALUATION BOARD LAYOUT Figure 97. Assembly—Primary Side Figure 98. Assembly—Secondary Side Rev Page ...
Page 49
AD9704/AD9705/AD9706/AD9707 Figure 99. Layer 1—Primary Side Figure 100. Layer 4—Secondary Side Rev Page ...
Page 50
AD9704/AD9705/AD9706/AD9707 Figure 101. Layer 2—Ground Plane Figure 102. Layer 3—Power Plane Rev Page ...
Page 51
... MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 AD9704BCPZ −40°C to +85°C 1 AD9704BCPZRL7 −40°C to +85°C 1 AD9705BCPZ −40°C to +85°C 1 AD9705BCPZRL7 −40°C to +85°C AD9706BCPZ 1 −40°C to +85°C 1 AD9706BCPZRL7 −40°C to +85°C ...
Page 52
AD9704/AD9705/AD9706/AD9707 NOTES ©2006–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05926-0-4/07(A) Rev Page ...