CS4365-CQZ Cirrus Logic Inc, CS4365-CQZ Datasheet - Page 21
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CS4365-CQZ
Manufacturer Part Number
CS4365-CQZ
Description
IC DAC 6CH 114DB 192KHZ 48LQFP
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS4365-CQZ.pdf
(52 pages)
Specifications of CS4365-CQZ
Package / Case
48-LQFP
Number Of Bits
24
Data Interface
Serial
Number Of Converters
6
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
390mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Conversion Rate
216 KSPS
Resolution
24 bit
Interface Type
Serial
Operating Supply Voltage
5 V
Operating Temperature Range
+ 85 C
Maximum Power Dissipation
390 mW
Mounting Style
SMD/SMT
Number Of Dac Outputs
6
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1779 - EVALUATION BOARD FOR CS4365
Settling Time
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1060
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS4365-CQZ
Manufacturer:
NS
Quantity:
301
Company:
Part Number:
CS4365-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
DS670F2
4. APPLICATIONS
The CS4365 serially accepts two’s complement formatted PCM data at standard audio sample rates including 48,
44.1 and 32 kHz in SSM, 96, 88.2 and 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via
the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input
on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer. For more information on serial
audio interfaces, see Cirrus Application Note AN282, “The 2-Channel Serial Audio Interface: A Tutorial.”
The CS4365 can be configured in Hardware Mode by the M0, M1, M2, M3 and M4 pins and in Software Mode
through I²C or SPI.
4.1
Sample Rate
Sample Rate
Sample Rate
Master Clock
MCLK/LRCK must be an integer ratio as shown in
frequency at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio and
speed mode is detected automatically during the initialization sequence by counting the number of MCLK
transitions during a single LRCK period and by detecting the absolute speed of MCLK. Internal dividers are
then set to generate the proper internal clocks.
and the required MCLK and LRCK frequencies. Please note there is no required phase relationship, but
MCLK, LRCK and SCLK must be synchronous.
(kHz)
(kHz)
(kHz)
176.4
44.1
88.2
192
32
48
64
96
= Denotes clock ratio and sample rate combinations which are NOT supported under auto speed-
mode detection. Please see
= Denotes clock ratio and sample rate combinations which are NOT supported under auto speed-
mode detection. Please see
= Denotes clock ratio and sample rate combinations which are NOT supported under auto speed-
mode detection. Please see
12.2880
11.2896
8.1920
256x
11.2896
12.2880
11.2896
12.2880
8.1920
128x
64x
Table 2. Double-Speed Mode Standard Frequencies
Table 1. Single-Speed Mode Standard Frequencies
Table 3. Quad-Speed Mode Standard Frequencies
12.2880
16.9344
18.4320
384x
12.2880
16.9344
18.4320
16.9344
18.4320
192x
96x
“Switching Characteristics - PCM” on page
“Switching Characteristics - PCM” on page
“Switching Characteristics - PCM” on page
Tables 1
16.3840
22.5792
24.5760
512x
Tables 1
MCLK (MHz)
MCLK (MHz)
MCLK (MHz)
16.3840
22.5792
24.5760
-
256x
22.5792
24.5760
3
128x
illustrate several standard audio sample rates
- 3. The LRCK frequency is equal to Fs, the
24.5760
33.8688
36.8640
768x
24.5760
33.8688
36.8640
384x
33.8688
36.8640
192x
32.7680
45.1584
49.1520
1024x
15.
15.
15.
49.1520
32.7680
45.1584
45.1584
49.1520
512x
CS4365
256x
36.8640
1152x
21