CS4365-CQZ Cirrus Logic Inc, CS4365-CQZ Datasheet - Page 38

IC DAC 6CH 114DB 192KHZ 48LQFP

CS4365-CQZ

Manufacturer Part Number
CS4365-CQZ
Description
IC DAC 6CH 114DB 192KHZ 48LQFP
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS4365-CQZ

Package / Case
48-LQFP
Number Of Bits
24
Data Interface
Serial
Number Of Converters
6
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
390mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Conversion Rate
216 KSPS
Resolution
24 bit
Interface Type
Serial
Operating Supply Voltage
5 V
Operating Temperature Range
+ 85 C
Maximum Power Dissipation
390 mW
Mounting Style
SMD/SMT
Number Of Dac Outputs
6
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1779 - EVALUATION BOARD FOR CS4365
Settling Time
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1060

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Manufacturer
Quantity
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Manufacturer:
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Manufacturer:
Cirrus Logic Inc
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38
6.5
6.5.1 Interpolation Filter Select (FILT_SEL)
6.6
6.6.1 Invert Signal Polarity (Inv_xx)
6.7
6.7.1 Mute Pin Control (MUTEC1, MUTEC0)
Reserved
Reserved
MUTEC1
0
0
0
7
7
7
Filter Control (address 05h)
Invert Control (address 06h)
Group Control (address 07h)
Function:
When set to 0 (default), the Interpolation Filter has a fast roll-off.
When set to 1, the Interpolation Filter has a slow roll-off.
The specifications for each filter can be found in the Analog characteristics table, and response plots can
be found in
Function:
When set to 1, this bit inverts the signal polarity of channel xx.
When set to 0 (default), this function is disabled.
Default = 00
00 - Six mute control signals
01, 10 - One mute control signal
11 - Three mute control signals
Function:
Selects how the internal mute control signals are routed to the MUTEC1 through MUTEC6 pins. When
set to ‘00’, there is one mute control signal for each channel: AOUT1A on MUTEC1, AOUT1B on
MUTEC2, etc. When set to ‘01’ or ‘10’, there is a single mute control signal on the MUTEC1 pin. When
set to ‘11’, there are three mute control signals, one for each stereo pair: AOUT1A and AOUT1B on
MUTEC1, AOUT2A and AOUT2B on MUTEC2, and AOUT3A and AOUT3B on MUTEC3.
Reserved
Reserved
MUTEC0
6
0
6
0
6
0
Figures 24
Reserved
Reserved
INV_B3
to 47.
5
0
5
0
5
0
Reserved
P1_A=B
INV_A3
0
0
0
4
4
4
Reserved
P2_A=B
INV_B2
3
0
3
0
3
0
Reserved
P3_A=B
INV_A2
2
0
2
0
2
0
Reserved
Reserved
INV_B1
0
0
0
1
1
1
SNGLVOL
FILT_SEL
CS4365
INV_A1
DS670F2
0
0
0
0
0
0

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