CS4382A-CQZ Cirrus Logic Inc, CS4382A-CQZ Datasheet - Page 29

IC DAC 8CH 114DB 192KHZ 48LQFP

CS4382A-CQZ

Manufacturer Part Number
CS4382A-CQZ
Description
IC DAC 8CH 114DB 192KHZ 48LQFP
Manufacturer
Cirrus Logic Inc
Datasheets

Specifications of CS4382A-CQZ

Package / Case
48-LQFP
Number Of Bits
24
Data Interface
Serial
Number Of Converters
8
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
680mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Conversion Rate
192 KSPS
Resolution
24 bit
Interface Type
Serial
Operating Supply Voltage
5 V
Operating Temperature Range
+ 85 C
Maximum Power Dissipation
390 mW
Mounting Style
SMD/SMT
Number Of Dac Outputs
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1524 - BOARD EVAL FOR CS4382A DAC
Settling Time
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1061
DS618F2
4.13
4.14
4.14.1 MAP Auto Increment
4.14.2 I²C Mode
Recommended Procedure for Switching Operational Modes
For systems where the absolute minimum in clicks and pops is required, it is recommended that the MUTE
bits are set prior to changing significant DAC functions (such as changing sample rates or clock sources).
The mute bits may then be released after clocks have settled and the proper modes have been set.
It is required to have the device held in reset if the minimum high/low time specs of MCLK cannot be met
during clock source changes.
Control Port Interface
The Control Port is used to load all the internal register settings in order to operate in Software Mode (see
the
audio sample rate. However, to avoid potential interference problems, the Control Port pins should remain
static if no operation is required.
The Control Port operates in one of two modes: I²C or SPI.
4.14.2.1 I²C Write
To write to the device, follow the procedure below while adhering to the Control Port Switching Specifica-
tions in
1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be
2. Wait for an acknowledge (ACK) from the part; then write to the memory address pointer, MAP. This
3. Wait for an acknowledge (ACK) from the part; then write the desired data to the register pointed to by
4. If the INCR bit (see
5. If the INCR bit is set to 0 and further I²C writes to other registers are desired, it is necessary to initiate
The device has MAP (memory address pointer) auto-increment capability enabled by the INCR bit (also
the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and
SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or
writes of successive registers.
In the I²C Mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial
Control Port clock, SCL (see
enables the user to alter the chip address (001100[AD0][R/W]) and should be tied to VLC or GND, as re-
quired, before powering up the device. If the device ever detects a high-to-low transition on the AD0/CS
pin after power-up, SPI Mode will be selected.
“Filter Plots” on page
001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth
bit of the address byte is the R/W bit.
byte points to the register to be written.
the MAP.
are written, then initiate a STOP condition to the bus.
a repeated START condition and follow the procedure detailed from step 1. If no further writes to other
registers are desired, initiate a STOP condition to the bus.
Section
2.
42). The operation of the Control Port may be completely asynchronous with the
Section
Figure 18
4.14.1) is set to 1, repeat the previous step until all the desired registers
for the clock to data relationship). There is no CS pin. Pin AD0
CS4382A
29

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