AD9763ASTZ Analog Devices Inc, AD9763ASTZ Datasheet - Page 12
![IC DAC 10BIT DUAL 125MSPS 48LQFP](/photos/6/59/65923/505-48-lqfp_sml.jpg)
AD9763ASTZ
Manufacturer Part Number
AD9763ASTZ
Description
IC DAC 10BIT DUAL 125MSPS 48LQFP
Manufacturer
Analog Devices Inc
Series
TxDAC+®r
Specifications of AD9763ASTZ
Data Interface
Parallel
Settling Time
35ns
Number Of Bits
10
Number Of Converters
2
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
450mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Resolution (bits)
10bit
Sampling Rate
125MSPS
Input Channel Type
Parallel
Supply Voltage Range - Analog
3V To 5.5V
Supply Voltage Range - Digital
2.7V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9763-EBZ - BOARD EVAL FOR AD9763
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9763ASTZ
Manufacturer:
ADI
Quantity:
180
Company:
Part Number:
AD9763ASTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD9763ASTZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD9763ASTZRL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD9763ASTZRL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD9763
THEORY OF OPERATION
FUNCTIONAL DESCRIPTION
Figure 22 shows a simplified block diagram of the AD9763. The
AD9763 consists of two DACs, each one with its own independent
digital control logic and full-scale output current control. Each
DAC contains a PMOS current source array capable of providing
up to 20 mA of full-scale current (I
The array is divided into 31 equal currents that make up the five
most significant bits (MSBs). The next four bits, or middle bits,
consist of 15 equal current sources whose value is 1/16
MSB current source. The remaining LSB is a binary weighted
fraction of the middle bit current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances the dynamic performance for multitone or low
amplitude signals and helps maintain the DAC high output
impedance (that is, >100 kΩ).
I
Figure 21. Basic AC Characterization Test Setup for AD9763, Testing Port 1 in Dual Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ2
REF
R
SET
2kΩ
1
I
REF
1
2
R
2kΩ
SET
0.1µF
R
DCOM
RETIMED CLOCK OUTPUT*
SET
DVDD
R
2kΩ
0.1µF
1
2kΩ
SET
2
2
LECROY 9210
GENERATOR
FSADJ1
REFIO
FSADJ2
PULSE
FSADJ1
REFIO
FSADJ2
GAINCTRL
GAINCTRL
1.2V REF
1.2V REF
OUTFS
AD9763
AD9763
50Ω
WRT1/
IQWRT
IQWRT
WRT1/
CURRENT
CURRENT
).
SOURCE
CURRENT
SOURCE
CURRENT
SOURCE
ARRAY
ARRAY
SOURCE
PMOS
PMOS
ARRAY
ARRAY
AVDD
PMOS
PMOS
AVDD
5V
CHANNEL 1 LATCH
5V
CHANNEL 1 LATCH
DB0 TO DB9
DB0 TO DB9
TEKTRONIX
w/OPTION 4
AWG-2021
DIGITAL
DATA
DIGITAL DATA INPUTS
MULTIPLEXING LOGIC
DIVIDER
Figure 22. Simplified Block Diagram
DIVIDER
MULTIPLEXING LOGIC
th
CLK
CLK
of an
LATCH
DAC 1
LATCH
DAC 1
Rev. D | Page 12 of 32
CLK1/IQCLK
CLK1/IQCLK CLK2/IQRESET
LATCH
DAC 2
LATCH
DAC 2
CHANNEL 2 LATCH
CHANNEL 2 LATCH
DB0 TO DB9
DB0 TO DB9
*AWG2021 CLOCK RETIMED SUCH THAT
DIGITAL DATA TRANSITIONS ON FALLING
EDGE OF 50% DUTY CYCLE CLOCK.
SWITCHES FOR
SWITCHES FOR
SWITCHES FOR
SWITCHES FOR
SEGMENTED
SEGMENTED
SEGMENTED
SEGMENTED
CLK2/IQRESET
All of these current sources are switched to one or the other of
the two output nodes (I
current switches. The switches are based on a new architecture
that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the
differential current switches.
The analog and digital sections of the AD9763 have separate
power supply inputs (AVDD and DVDD) that can operate
independently over a 3.3 V to 5 V range. The digital section is
capable of operating up to a 125 MSPS clock rate and consists of
edge triggered latches and segment decoding logic circuitry.
The analog section includes the PMOS current sources, the
associated differential switches, a 1.20 V band gap voltage
reference, and two reference control amplifiers.
DAC1
DAC2
DAC1
DAC2
WRT2/
IQSEL
WRT2/
IQSEL
SWITCH
SWITCH
SWITCH
SWITCH
ACOM
LSB
LSB
LSB
LSB
SLEEP
SLEEP
DCOM
DCOM
ACOM
I
I
I
I
DVDD
MODE
OUTA1
OUTB1
OUTA2
OUTB2
I
I
I
I
MODE
DVDD
OUTA1
OUTB1
OUTA2
OUTB2
OUTA
5V
or I
V
50Ω
OUT
5V
V
OUTB
R
2B
50Ω
DIFF
L
2B
50Ω
V
) via PMOS differential
B
= V
CIRCUITS
OUT
T1-1T
MINI
OUT
R
50Ω
2A
L
A – V
2A
V
OUT
OUT
R
50Ω
1B
TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
L
B
1B
V
OUT
R
50Ω
1A
L
1A