AD9763ASTZ Analog Devices Inc, AD9763ASTZ Datasheet - Page 15

• Manufacturer Part Number: AD9763ASTZ
• Description: IC DAC 10BIT DUAL 125MSPS 48LQFP
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9763ASTZ

• Data Interface: Parallel
• Settling Time: 35ns
• Number Of Bits: 10
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 450mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 10bit
• Sampling Rate: 125MSPS
• Input Channel Type: Parallel
• Supply Voltage Range - Analog: 3V To 5.5V
• Supply Voltage Range - Digital: 2.7V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9763-EBZ - BOARD EVAL FOR AD9763
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

DIGITAL INPUTS
The digital inputs of the AD9763 consist of two independent
channels. For the dual port mode, each DAC has its own
dedicated 10-bit data port, WRT line, and CLK line. In the
interleaved timing mode, the function of the digital control pins
changes as described in the Interleaved Mode Timing section.
The 10-bit parallel data inputs follow straight binary coding
where DB9 is the most significant bit (MSB) and DB0 is the
least significant bit (LSB). I
current when all data bits are at Logic 1. I
plementary output with the full-scale current split between the
two outputs as a function of the input code.
The digital interface is implemented using an edge triggered
master/slave latch. The DAC outputs are updated following
either the rising edge, or every other rising edge of the clock,
depending on whether dual or interleaved mode is being used.
The DAC outputs are designed to support a clock rate as high as
125 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transition
edges can affect digital feedthrough and distortion performance.
Best performance is typically achieved when the input data
transitions on the falling edge of a 50% duty cycle clock.
DAC TIMING
The AD9763 can operate in two timing modes, dual and
interleaved, as described in the following sections.
Dual Port Mode Timing
When the MODE pin is at Logic 1, the AD9763 operates in dual
port mode (refer to Figure 21). The AD9763 functions as two
distinct DACs. Each DAC has its own completely independent
digital input and control lines.
The AD9763 features a double buffered data path. Data enters
the device through the channel input latches. This data is then
transferred to the DAC latch in each signal path. Once the data
is loaded into the DAC latch, the analog output settles to its
new value.
For general consideration, the WRT lines control the channel
input latches and the CLK lines control the DAC latches. Both
sets of latches are updated on the rising edge of their respective
control signals.
The rising edge of CLK should occur before or simultaneously with
the rising edge of WRT. If the rising edge of CLK occurs after the
rising edge of WRT, a 2 ns minimum delay should be main-
tained from the rising edge of WRT to the rising edge of CLK.
Timing specifications for dual port mode are shown in Figure 25
and Figure 26.
OUTA
produces a full-scale output
OUTB
B
produces a com-
Rev. D | Page 15 of 32
Interleaved Mode Timing
When the MODE pin is at Logic 0, the AD9763 operates in
interleaved mode (refer to Figure 27). WRT1 now functions as
IQWRT and CLK1 functions as IQCLK. WRT2 functions as
IQSEL and CLK2 functions as IQRESET.
Data enters the device on the rising edge of IQWRT. The
logic level of IQSEL steers the data to either Channel Latch 1
(IQSEL = 1) or to Channel Latch 2 (IQSEL = 0). For proper
operation, IQSEL should only change state when IQWRT and
IQCLK are low.
When IQRESET is high, IQCLK is disabled. When IQRESET
goes low, the following rising edge on IQCLK updates both DAC
latches with the data present at their inputs. In the interleaved
mode, IQCLK is divided by 2 internally. Following this first
rising edge, the DAC latches are only updated on every other
rising edge of IQCLK. In this way, IQRESET can be used to
synchronize the routing of the data to the DACs.
As with the dual port mode, IQCLK should occur before or
simultaneously with IQWRT.
IQWRT
IQSEL
WRT1/WRT2
DATA IN, PORT 1
CLK1/CLK2
WRT1/WRT2
INTERLEAVED
CLK1/CLK2
DATA IN
DATA IN
I
I
OUTA
OUTB
IQRESET
I
I
OR
OUTA
OUTB
OR
IQCLK
Figure 27. Latch Structure in Interleaved Mode
D1
Figure 25. Dual Mode Timing
Figure 26. Dual Mode Timing
xx
D2
PORT 1
PORT 2
LATCH
LATCH
INPUT
INPUT
÷2
t
S
D1
D3
DAC1
LATCH
DAC2
LATCH
t
PD
D2
D4
DAC1
DAC2
t
H
t
t
LPW
CPW
DEINTERLEAVED
DATA OUT
D3
D5
AD9763
D4