AD9772AASTZ Analog Devices Inc, AD9772AASTZ Datasheet - Page 20

• Manufacturer Part Number: AD9772AASTZ
• Description: IC DAC 14BIT 160MSPS 48-LQFP
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9772AASTZ

• Data Interface: Parallel
• Settling Time: 11ns
• Number Of Bits: 14
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 272mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 14bit
• Sampling Rate: 160MSPS
• Input Channel Type: Parallel
• Supply Voltage Range - Analog: 3.1V To 3.5V
• Supply Current: 37mA
• Digital Ic Case Style: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9772A-EB - BOARD EVAL FOR AD9772A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9772A
The PLL clock multiplier has two modes of operation. It can be
enabled for less demanding applications, providing a reference
clock meeting the minimum specified input data rate of 6 MSPS.
Alternatively, it can be disabled for applications below this data
rate or for applications requiring higher phase noise performance.
In this case, a reference clock must be provided at twice the input
data rate (that is, 2 × f
or at four times the input data rate (that is, 4 × f
stuffing option selected. Note that multiple AD9772A devices
can be synchronized in either mode if driven by the same reference
clock because the PLL clock multiplier, when enabled, ensures
synchronization. RESET can be used for synchronization if the
PLL clock multiplier is disabled.
Figure 30 shows the proper configuration used to enable the
PLL clock multiplier. In this case, the external clock source is
applied to CLK+ (and/or CLK−) and the PLL clock multiplier is
fully enabled by connecting PLLVDD to CLKVDD.
The settling/acquisition time characteristics of the PLL are also
dependent on the divide-by-N ratio as well as the input data
rate. In general, the acquisition time increases with increasing
data rate (for fixed divide-by-N ratio) or with an increasing
divide-by-N ratio (for fixed input data rate).
Because the VCO can operate over a 96 MHz to 400 MHz
range, the prescaler divide-by-ratio following the VCO must be
set according to Table 10 for a given input data rate (that is,
f
general, the best phase noise performance for any prescaler
setting is achieved with the VCO operating near its maximum
output frequency of 400 MHz. Note that the divide-by-N ratio
also depends on whether the zero-stuffing option is enabled
because this option requires the DAC to operate at 4× the input
data rate. The divide-by-N ratio is set by DIV1 and DIV0.
With the PLL clock multiplier enabled, PLLLOCK serves as an
active high control output that can be monitored upon system
power-up to indicate that the PLL is successfully locked to the
input clock. Note that when the PLL clock multiplier is not
locked, PLLLOCK toggles between logic high and low in an
asynchronous manner until locking is finally achieved. As a
result, it is recommended that PLLLOCK, if monitored, be
sampled several times to detect proper locking 100 ms after
power-up.
Table 10. Recommended Prescaler Divide-by-N Ratio Settings
f
(MSPS)
48 to 160
24 to 100
12 to 50
6 to 25
24 to 100
12 to 50
6 to 25
3 to 12.5
DATA
DATA
) to ensure optimum phase noise and successful locking. In
MOD1
0
0
0
0
1
1
1
1
DATA
) without the zero-stuffing option selected
DIV1
0
0
1
1
0
0
1
1
DIV0
0
1
0
1
0
1
0
1
Divide-by-N Ratio
1
2
4
8
1
2
4
8
DATA
) with the zero-
Rev. C | Page 20 of 40
As previously stated, applications requiring input data rates
below 6 MSPS must disable the PLL clock multiplier and
provide an external reference clock. However, for applications
already containing a low phase noise (that is, low jitter) reference
clock that is twice (or four times) the input data rate, users should
consider disabling the PLL clock multiplier to achieve the best SNR
performance from the AD9772A. Note that the SFDR performance
and wideband noise performance of the AD9772A remain
unaffected with or without the PLL clock multiplier enabled.
The effects of phase noise on the AD9772A SNR performance
become more noticeable at higher reconstructed output fre-
quencies and signal levels. Figure 31 compares the phase noise
of a full-scale sine wave at exactly f
(and therefore carrier frequencies) with the optimum DIV1 and
DIV0 settings. The effects of phase noise, and its effect on a
signal’s CNR performance, become even more evident at higher
IF frequencies, as shown in Figure 32. In both instances, it is the
narrow-band phase noise that limits the CNR performance.
To disable the PLL clock multiplier, connect PLLVDD to
PLLCOM as shown in Figure 33. LPF can then remain open
because this portion of the PLL circuitry is disabled. The
Figure 31. Phase Noise of PLL Clock Multiplier with a Full-Scale Sine Wave at
Exactly f
Figure 32. Direct IF Mode Reveals Phase Noise Degradation with and
Without PLL Clock Multiplier (IF = 125 MHz and f
–100
–110
–110
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–30
–50
–70
–90
Settings Using the Rohde & Schwarz FSEA30, RBW = 30 kHz
10
0
OUT
120
0
= f
PLL ENABLED,
PLL ENABLED,
DATA
/4 for Different f
122
1
FREQUENCY OFFSET (MHz)
f
f
DATA
DATA
PLL ENABLED,
FREQUENCY (MHz)
124
2
= 50MSPS
= 160MSPS
PLL ENABLED,
DATA
PLL ENABLED,
Settings with Optimum DIV0/DIV1
DATA
126
3
/4 for different data rates
f
DATA
f
DATA
= 100MSPS
f
DATA
DATA
128
= 75MSPS
4
= 100 MSPS)
= 50MSPS
130
5