AD9772AASTZ Analog Devices Inc, AD9772AASTZ Datasheet - Page 25
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AD9772AASTZ
Manufacturer Part Number
AD9772AASTZ
Description
IC DAC 14BIT 160MSPS 48-LQFP
Manufacturer
Analog Devices Inc
Series
TxDAC+®r
Datasheet
1.AD9772AASTZ.pdf
(40 pages)
Specifications of AD9772AASTZ
Data Interface
Parallel
Settling Time
11ns
Number Of Bits
14
Number Of Converters
1
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
272mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Resolution (bits)
14bit
Sampling Rate
160MSPS
Input Channel Type
Parallel
Supply Voltage Range - Analog
3.1V To 3.5V
Supply Current
37mA
Digital Ic Case Style
QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9772A-EB - BOARD EVAL FOR AD9772A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9772AASTZ
Manufacturer:
TI
Quantity:
1 756
Company:
Part Number:
AD9772AASTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD9772AASTZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD9772AASTZRL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD9772AASTZRL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
The quality of the clock and data input signals is important in
achieving the optimum performance. The external clock driver
circuitry should provide the AD9772A with a low jitter clock
input, which meets the minimum/maximum logic levels while
providing fast edges. Although fast clock edges help minimize
jitter manifesting as phase noise on a reconstructed waveform,
the high gain-bandwidth product of the AD9772A differential
comparator can tolerate sine wave inputs as low as 0.5 V p-p,
with minimal degradation in its output noise floor.
Digital signal paths should be kept short, and run lengths
should match to avoid propagation delay mismatch. The
insertion of a low value resistor network (that is, 50 Ω to 200 Ω)
between the AD9772A digital inputs and driver outputs may be
helpful in reducing overshooting and ringing at the digital
inputs that contribute to data feedthrough.
SLEEP MODE OPERATION
The AD9772A has a sleep function that turns off the output current
and reduces the analog supply current to less than 6 mA over the
specified supply range of 3.1 V to 3.5 V. This mode can be activated
by applying a Logic Level 1 to the SLEEP pin. The AD9772A
takes less than 50 ns to power down and then approximately 15 μs
to power up.
POWER DISSIPATION
The power dissipation, P
several factors, including
•
•
•
•
The power supply voltages (AVDD, PLLVDD, CLKVDD,
and DVDD)
The full-scale current output (I
The update rate (f
The reconstructed digital input waveform
ECL/PECL
Figure 44. Differential Clock Interface
AD9772A
DATA
0.1µF
0.1µF
0.1µF
D
, of the AD9772A is dependent on
)
1kΩ
1kΩ
1kΩ
1kΩ
OUTFS
)
CLK+
CLKVDD
CLK–
CLKCOM
Rev. C | Page 25 of 40
The power dissipation is directly proportional to the analog
supply current, I
is directly proportional to I
Conversely, I
waveform and f
scale sine wave output ratios (f
with DVDD = 3.3 V. The supply current from CLKVDD and
PLLVDD is relatively insensitive to the digital input waveform
but directly proportional to the update rate, as shown in Figure 46.
100
15
10
90
80
70
60
50
40
30
20
10
25
20
5
0
0
0
0
DVDD
Figure 45. I
DATA
AVDD
Figure 46. I
is dependent on both the digital input
0.1
. Figure 45 shows I
, and the digital supply current, I
50
DVDD
RATIO (
PLLVDD
OUTFS
0.2
f
vs. Ratio @ DVDD = 3.3 V
DATA
OUT
and I
f
100
and is not sensitive to f
f
f
f
OUT
(MSPS)
DATA
DATA
DATA
f
f
f
/f
DATA
DATA
DATA
DATA
/
f
CLKVDD
DATA
0.3
I
= 160MSPS
= 125MSPS
= 100MSPS
CLKVDD
DVDD
= 65MSPS
= 50MSPS
= 25MSPS
) for various update rates
)
vs. f
as a function of full-
I
DATA
PLLVDD
150
0.4
AD9772A
DVDD
DATA
200
0.5
. I
.
AVDD