CS4385-DQZ Cirrus Logic Inc, CS4385-DQZ Datasheet - Page 30

IC DAC 8CH 114DB 192KHZ 48LQFP

CS4385-DQZ

Manufacturer Part Number
CS4385-DQZ
Description
IC DAC 8CH 114DB 192KHZ 48LQFP
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS4385-DQZ

Data Interface
Serial
Number Of Bits
24
Number Of Converters
8
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
520mW
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Resolution (bits)
24bit
Sampling Rate
192kSPS
Input Channel Type
Serial
Supply Voltage Range - Analog
4.75V To 5.25V
Supply Current
84mA
Digital Ic Case Style
QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1154 - BOARD EVAL FOR CS4385 DAC
Settling Time
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
598-1649

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CS4385
Figure 24. Recommended Output Filter
4.11
The MUTEC Outputs
The MUTEC1 and MUTEC234 pins have an auto-polarity detect feature. The MUTEC output pins are high
impedance at the time of reset. The external mute circuitry needs to be self-biased into an active state in
order to be muted during reset. Upon release of reset, the CS4385 will detect the status of the MUTEC pins
(high or low) and will then select that state as the polarity to drive when the mutes become active. The ex-
ternal-bias voltage level that the MUTEC pins see at the time of release of reset must meet the “MUTEC
auto-detect input high/low voltage” specifications as outlined in the Digital Characteristics section.
Figure 25
shows a single example of both an active high and an active low mute drive circuit. In these de-
signs, the pull-up and pull-down resistors have been especially chosen to meet the input high/low threshold
when used with the MMUN2111 and MMUN2211 internal bias resistances of 10 kΩ. Use of the Mute Control
function is not mandatory, but recommended, for designs requiring the absolute minimum in extraneous
clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle chan-
nel noise/signal-to-noise ratios which are only limited by the external mute circuit.
30
DS671F2

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