CS4385-DQZ Cirrus Logic Inc, CS4385-DQZ Datasheet - Page 34

• Manufacturer Part Number: CS4385-DQZ
• Description: IC DAC 8CH 114DB 192KHZ 48LQFP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4385-DQZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 8
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 520mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 24bit
• Sampling Rate: 192kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Current: 84mA
• Digital Ic Case Style: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1154 - BOARD EVAL FOR CS4385 DAC
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1649

34
4.14.3 SPI Mode
4.15
4.15.1 INCR (Auto Map Increment Enable)
4.15.2 MAP4-0 (Memory Address Pointer)
INCR
7
0
Memory Address Pointer (MAP)
4.14.3.1 SPI Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifica-
tions in
1. Bring CS low.
2. The address byte on the CDIN pin must then be 00110000.
3. Write to the memory address pointer, MAP. This byte points to the register to be written.
4. Write the desired data to the register pointed to by the MAP.
5. If the INCR bit (see
6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring
In SPI Mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK
(see
is used to control SPI writes to the control port. When the device detects a high to low transition on the
AD0/CS pin after power-up, SPI Mode will be selected. All signals are inputs and data is clocked in on the
rising edge of CCLK.
Default = ‘0’
0 - Disabled
1 - Enabled
Default = ‘00000’
are written, then bring CS high.
CS high, and follow the procedure detailed from step 1. If no further writes to other registers are de-
sired, bring CS high.
Figure 27
Reserved
Section
6
0
for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and
1.
CS
CCLK
C DIN
Reserved
Section
5
0
Figure 27. Control Port Timing, SPI Mode
M AP = M em ory Address Pointer
ADDRESS
0011000
4.14.1) is set to 1, repeat the previous step until all the desired registers
CHIP
MAP4
4
0
R/W
MAP
MAP3
3
0
MSB
byte 1
DATA
MAP2
byte n
2
0
LSB
MAP1
1
0
CS4385
MAP0
DS671F2
0
0