AD5724RBREZ Analog Devices Inc, AD5724RBREZ Datasheet - Page 29

• Manufacturer Part Number: AD5724RBREZ
• Description: IC DAC 12BIT DSP/SRL 24TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5724RBREZ

• Data Interface: Serial
• Design Resources: Software Configurable 12-Bit Quad Channel Unipolar/Bipolar Voltage Output Using AD5724R (CN0085)
• Settling Time: 10µs
• Number Of Bits: 12
• Number Of Converters: 4
• Voltage Supply Source: Analog and Digital, Dual ±
• Power Dissipation (max): 310mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Resolution (bits): 12bit
• Sampling Rate: 1.1MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Digital: 2.7V To 5.5V
• Supply Current: 2.5mA
• Digital Ic Case Style: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWER CONTROL REGISTER
The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the
power and thermal status of the AD5724R/AD5734R/AD5754R. The power control register options are shown in Table 27 and Table 28.
Table 27. Programming the Power Control Register
MSB
R/ W
0
Table 28. Power Control Register Functions
Option
PU
PU
PU
PU
PU
TSD
OC
OC
OC
OC
A
B
C
D
REF
A
B
C
D
Zero
0
Description
DAC A power-up. When set, this bit places DAC A in normal operating mode. When cleared, this bit places DAC A in power-down
mode (default). After setting this bit to power DAC A, a power-up time of 10 μs is required. During this power-up time the DAC
register should not be loaded to the DAC output (see the Load DAC (LDAC) section). If the clamp enable bit of the control register
is cleared, DAC A powers down automatically on detection of an overcurrent, and PU
DAC B power-up. When set, this bit places DAC B in normal operating mode. When cleared, this bit places DAC B in power-down
mode (default). After setting this bit to power DAC B, a power-up time of 10 μs is required. During this power-up time the DAC
register should not be loaded to the DAC output (see the Load DAC(LDAC) section). If the clamp enable bit of the control register
is cleared, DAC B powers down automatically on detection of an overcurrent, and PU
DAC C power-up. When set, this bit places DAC C in normal operating mode. When cleared, this bit places DAC C in power-down
mode (default). After setting this bit to power DAC C, a power-up time of 10 μs is required. During this power-up time the DAC
register should not be loaded to the DAC output (see the Load DAC(LDAC) section). If the clamp enable bit of the control register
is cleared, DAC C powers down automatically on detection of an overcurrent, and PU
DAC D power-up. When set, this bit places DAC D in normal operating mode. When cleared, this bit places DAC D in power-down
mode (default). After setting this bit to power DAC D, a power-up time of 10 μs is required. During this power-up time the DAC
register should not be loaded to the DAC output (see the Load DAC(LDAC) section). If the clamp enable bit of the control register
is cleared, DAC D powers down automatically on detection of an overcurrent, and PU
Reference power-up. When set, this bit places the internal reference in normal operating mode. When cleared, this bit places the
internal reference in power-down mode (default).
Thermal shutdown alert. Read-only bit. In the event of an overtemperature situation, the four DACs are powered down and this
bit is set.
DAC A overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC A, this bit is set.
DAC B overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC B, this bit is set.
DAC C overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC C, this bit is set.
DAC D overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC D, this bit is set.
REG2
0
REG1
1
REG0
0
A2
0
A1
0
A0
0
DB15 to
DB11
X
Rev. C | Page 29 of 32
DB10
OC
D
DB9
OC
C
DB8
OC
B
DB7
OC
A
AD5724R/AD5734R/AD5754R
DB6
0
B
C
A
D
is cleared to reflect this.
is cleared to reflect this.
is cleared to reflect this.
is cleared to reflect this.
DB5
TSD
DB4
PU
REF
DB3
PU
D
DB2
PU
C
DB1
PU
B
LSB
DB0
PU
A