MT46V8M16TG-75Z:D TR Micron Technology Inc, MT46V8M16TG-75Z:D TR Datasheet - Page 51

• Manufacturer Part Number: MT46V8M16TG-75Z:D TR
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V8M16TG-75Z:D TR

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 750ps
• Maximum Clock Rate: 266MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 140mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

PDF: 09005aef816fd013/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN
Data from any READ burst may be truncated with a BURST TERMINATE command, as
shown in Figure 29 on page 56. The BURST TERMINATE latency is equal to the CL, that
is, the BURST TERMINATE command should be issued x cycles after the READ
command where x equals the number of desired data element pairs (pairs are required
by the 2n-prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE
command can be issued. If truncation is necessary, the BURST TERMINATE command
must be used, as shown in Figure 30 on page 57. The
t
defined in the section on WRITEs.) A READ burst may be followed by, or truncated with,
a PRECHARGE command to the same bank provided that auto precharge was not acti-
vated.
The PRECHARGE command should be issued x cycles after the READ command, where
x equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 31 on page 58. Following the PRECHARGE
command, a subsequent command to the same bank cannot be issued until both
and
last data elements.
DQSS (MAX) case has a longer bus idle time. (
t
RP have been met. Part of the row precharge time is hidden during the access of the
51
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
128Mb: x4, x8, x16 DDR SDRAM
DQSS [MIN] and
t
DQSS (NOM) case is shown; the
©2004 Micron Technology, Inc. All rights reserved.
t
DQSS [MAX] are
Operations
t
RAS