MT46V8M16TG-75Z:D TR Micron Technology Inc, MT46V8M16TG-75Z:D TR Datasheet - Page 61

• Manufacturer Part Number: MT46V8M16TG-75Z:D TR
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V8M16TG-75Z:D TR

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 750ps
• Maximum Clock Rate: 266MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 140mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Figure 34:
PDF: 09005aef816fd013/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN
x16 Data Output Timing –
DQ8–DQ15 and UDQS, collectively 6
DQ0–DQ7 and LDQS, collectively 6
Notes:
DQ (first data no longer valid) 4
DQ (first data no longer valid) 4
DQ (first data no longer valid) 7
DQ (first data no longer valid) 7
DQ (last data valid) 4
DQ (last data valid) 4
DQ (last data valid) 7
DQ (last data valid) 7
1.
2.
3. DQs transitioning after DQS transition define the
4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
5.
6. The data valid window is derived for each DQS transition and is
7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
t
t
transition, and ends with the last valid DQ transition.
byte, and UDQS defines the upper byte.
t
HP is the lesser of
DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
QH is derived from
UDQS 3
LDQS 3
CK#
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
DQ 7
DQ 7
DQ 7
DQ 7
DQ 7
DQ 7
CK
T1
t
DQSQ,
t
t HP
CL or
t
HP:
1
t
t
t
QH =
QH, and Data Valid Window
CH clock transition collectively when a bank is active.
61
t HP
t
1
HP -
t DQSQ
t QH 5
t DQSQ 2
T2
t QH 5
t
Data valid
2
QHS.
window
Data valid
T2
T2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
window
t HP
T2
T2
T2
1
t DQSQ
T2n
t QH 5
t DQSQ 2
128Mb: x4, x8, x16 DDR SDRAM
Data valid
t QH 5
window
2
t HP
T2n
t
T2n
Data valid
T2n
DQSQ window. LDQS defines the lower
window
1
T2n
T2n
T2n
T3
t DQSQ
t QH 5
t DQSQ 2
t QH 5
t HP
Data valid
2
window
1
Data valid
window
T3
T3
T3
T3
©2004 Micron Technology, Inc. All rights reserved.
T3
T3
t
T3n
QH -
t DQSQ 2
t DQSQ
t QH 5
t QH 5
t HP
t
DQSQ.
1
Data valid
window
Data valid
2
window
T3n
T3n
T4
T3n
T3n
T3n
T3n
Operations