NH82801FB S L89L Intel, NH82801FB S L89L Datasheet - Page 14

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NH82801FB S L89L

Manufacturer Part Number
NH82801FB S L89L
Description
Manufacturer
Intel
Datasheet

Specifications of NH82801FB S L89L

Mounting
Surface Mount
Lead Free Status / Rohs Status
Compliant
5.
Problem:
Implication:
Workaround:
Status:
6.
Problem:
Implication:
Workaround:
Status:
7.
Problem:
Implication:
Workaround:
Status:
8.
Problem:
Implication:
Workaround:
Status:
14
Intel
If a SATA device sends less than a 5 DWord Register Device-to-Host FIS, the ICH6 will correctly
respond with RERR but may not be able to accept any further FISes from the device.
SATA bus will hang.
The AHCI driver shall reset the bus by sending COMRESET, per the AHCI spec.
No Fix. For steppings affected, see the Summary Tables of Changes.
Intel
ICH6 may not properly complete non-DWord aligned locked cycles to LPC.
System Hang.
None.
No Fix. For steppings affected, see the Summary Tables of Changes.
Intel
ICH6 internal devices or devices connected to the ICH6 may experience additional completion
delays of up to 40 usec.
No end user functional impact expected.
None.
Fixed in B-2 stepping. For steppings affected, see the Summary Tables of Changes.
Intel
The ICH6 SATA transmit buffers have been designed to maximize performance and robustness
over a variety of routing scenarios. As a result, the ICH6 Serial ATA (SATA) transmit signaling
voltage levels may exceed the maximum motherboard TX connector and device RX connector
voltage specifications (section 6.6.2 of SATA Specification, rev 1.0a).
None known.
None.
No Fix. For steppings affected, see the Summary Tables of Changes.
Note: This only applies while operating in AHCI mode.
Note: No known devices use Register Device-to-Host FIS sizes less than 5 DWords, as these
are not allowed by the Serial ATA Specification, rev 1.0a.
This issue has only been replicated using a synthetic test environment and has not been
reported using commercially available hardware/software.
Most ICH6 devices are buffered adequately to withstand an additional 40 usec delay.
The UHCI (Full-speed only) may experience underruns and PCI may experience downstream
request delays. Both implications are allowable their respective industry specifications.
®
®
®
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ICH6 Improper Length Register Device-to-Host FIS
ICH6 Split Lock LPC Cycle
ICH6 Completion Delays
ICH6 SATA Signal Voltage Level
Intel® ICH6 Family Specification Update

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