EVAL-ADN2816EB Analog Devices Inc, EVAL-ADN2816EB Datasheet - Page 18

• Manufacturer Part Number: EVAL-ADN2816EB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADN2816EB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

ADN2816
Additional Features Available via the I
Coarse Data Rate Readback
The data rate can be read back over the I
approximately ±10% without the need of an external reference
clock. A 9-bit register, COARSE_RD[8:0], can be read back
when LOL is deasserted. The eight MSBs of this register are the
contents of the RATE[7:0] register. The LSB of the
COARSE_RD register is Bit MISC[0].
Table 13 provides coarse data rate readback to within ±10%.
2
C interface to
2
C Interface
Rev. A | Page 18 of 24
System Reset
A frequency acquisition can be initiated by writing a 1 followed
by a 0 to the I
frequency acquisition while keeping the ADN2816 in the
operating mode that it was previously programmed to in
Registers CTRL[A], CTRL[B], and CTRL[C].
2
C Register Bit CTRLB[5]. This initiates a new