EVAL-ADN2816EB Analog Devices Inc, EVAL-ADN2816EB Datasheet - Page 9

• Manufacturer Part Number: EVAL-ADN2816EB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADN2816EB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

I
SDA
SCK
2
C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
START BIT
S = START BIT
A(S) = ACKNOWLEDGE BY SLAVE
S
S
SLAVE ADDR, LSB = 0 (WR)
SDA
SCK
A6
SLAVE ADDRESS
S
t
F
A5
S
SLAVE ADDR, LSB = 0 (WR) A(S)
SLADDR[4...0]
t
t
LOW
HD;STA
MSB = 1
1
A(S)
t
SET BY
PIN 19
HD;DAT
SUB ADDR
t
SLAVE ADDRESS [6...0]
R
A5
t
SU;DAT
WR
P = STOP BIT
A(M) = ACKNOWLEDGE BY MASTER
Figure 6. Slave Address Configuration
Figure 10. I
Figure 9. I
0
Figure 7. I
Figure 8. I
A(S)
ACK
t
SUB ADDR
S
HIGH
Rev. A | Page 9 of 24
t
SUB ADDRESS
F
2
0
2
2
C Data Transfer Timing
2
SLAVE ADDR, LSB = 1 (RD)
C Port Timing Diagram
C Write Data Transfer
C Read Data Transfer
A7
SUB ADDR[6...1]
t
SU;STA
0
A(S)
DATA
0
A0
S
A(S)
A(M) = LACK OF ACKNOWLEDGE BY MASTER
t
ACK
SU;STO
0
A(S) DATA A(M)
t
HD;STA
0 = WR
1 = RD
R/W
CTRL.
D7
DATA
X
DATA
P
DATA[6...1]
A(S)
t
BUF
t
R
P
S
DATA
D0
A(M)
ACK
ADN2816
P
STOP BIT
P