AD7847BRZ Analog Devices Inc, AD7847BRZ Datasheet - Page 11

• Manufacturer Part Number: AD7847BRZ
• Description: IC DAC 12BIT DUAL MULT 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7847BRZ

• Data Interface: Parallel
• Settling Time: 4µs
• Number Of Bits: 12
• Number Of Converters: 2
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resolution (bits): 12bit
• Input Channel Type: Parallel
• Supply Voltage Range - Analogue: ± 14.25V To ± 15.75V
• Supply Current: 8mA
• Digital Ic Case Style: SOIC
• No. Of Pins: 24
• Number Of Channels: 2
• Resolution: 12b
• Conversion Rate: 250KSPS
• Interface Type: Parallel
• Single Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (typ): ±15V
• Architecture: Segment
• Power Supply Requirement: Dual
• Output Type: Voltage
• Integral Nonlinearity Error: ±0.5LSB
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): ±14.25V
• Dual Supply Voltage (max): ±15.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Package Type: SOIC W
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Compliant

AD7847–MC68000 Interface
Figure 21 shows an interface between the AD7847 and the
MC68000. Once again a single MOVE instruction loads the
12-bit word into the selected DAC latch. CSA and CSB are
AND-gated to provide a DTACK signal when either DAC
latch is selected.
AD7847–TMS320C10 Interface
Figure 22 shows an interface between the AD7847 and the
TMS320C10 DSP processor. A single OUT instruction loads
the 12-bit word into the selected DAC latch.
TMS320C10
MC68000
8086
DTACK
AD15
LDS
R/W
ALE
AD0
A23
D15
MEN
WR
AS
D0
A1
A11
D15
WE
D0
A0
ADDITIONAL PINS OMITTED FOR CLARITY
ADDITIONAL PINS OMITTED FOR CLARITY
ADDITIONAL PINS OMITTED FOR CLARITY
LATCH
16 BIT
ADDRESS/DATA BUS
ADDRESS BUS
ADDRESS BUS
EN
EN
ADDRESS
ADDRESS
DECODE
DECODE
ADDRESS BUS
DATA BUS
DATA BUS
ADDRESS
DECODE
CSB
CSA
CSB
WR
DB11
DB0
WR
CSA
WR
DB11
DB0
CSA
CSB
DB11
DB0
AD7847
AD7847
AD7847
MICROPROCESSOR INTERFACING–AD7837
Figures 23 to 25 show the AD7837 configured for interfacing to
microprocessors with 8-bit data bus systems. In all cases, data is
right-justified and the AD7837 is memory-mapped with the two
lowest address lines of the microprocessor address bus driving
the A0 and A1 inputs of the AD7837. Five separate memory
addresses are required, one for the each MS latch and one for
each LS latch and one for the common LDAC input. Data is
written to the respective input latch in two write operations.
Either high byte or low byte data can be written first to the
input latch. A write to the AD7837 LDAC address transfers the
data from the input latches to the respective DAC latches and
updates both analog outputs. Alternatively, the LDAC input
can be asynchronous and can be common to several AD7837s
for simultaneous updating of a number of voltage channels.
AD7837–8051/8088 Interface
Figure 23 shows the connection diagram for interfacing the
AD7837 to both the 8051 and the 8088. On the 8051, the
signal PSEN is used to enable the address decoder while DEN
is used on the 8088.
AD7837–MC68008 Interface
An interface between the AD7837 and the MC68008 is shown
in Figure 24. In the diagram shown, the LDAC signal is derived
from an asynchronous timer but this can be derived from the
address decoder as in the previous interface diagram.
PSEN OR DEN
8051/8088
MC68008
DTACK
R/W
ALE
AD7
AD0
A15
A19
WR
DS
AS
A0
D7
D0
A8
ADDITIONAL PINS OMITTED FOR CLARITY
ADDITIONAL PINS OMITTED FOR CLARITY
OCTAL
LATCH
ADDRESS/DATA BUS
ADDRESS BUS
EN
ADDRESS BUS
ADDRESS
DECODE
EN
ADDRESS
DECODE
DATA BUS
AD7837/AD7847
TIMER
LDAC
WR
DB7
DB0
CS
CS
LDAC
WR
DB7
DB0
AD7837
AD7837
A0 A1
A0 A1