FW82546GB S L75S Intel, FW82546GB S L75S Datasheet - Page 19
![no-image](/images/manufacturer_photos/0/3/336/intel_sml.jpg)
FW82546GB S L75S
Manufacturer Part Number
FW82546GB S L75S
Description
Manufacturer
Intel
Datasheet
1.FW82546GB_S_L75S.pdf
(54 pages)
Specifications of FW82546GB S L75S
Operating Supply Voltage (typ)
1.5/2.5/3.3V
Operating Supply Voltage (min)
1.43/2.38/3V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
364
Lead Free Status / Rohs Status
Not Compliant
3.4
3.5
3.5.1
3.5.2
Datasheet
Flash Interface Signals
Miscellaneous Signals
LED Signals
Software Definable Signals
FL_ADDR
[18:0]
FL_CS#
FL_OE#
FL_WE#
FL_DATA
[7:2]
FL_DATA
[1:0]/
LAN_DISA
BLE#
LED1/ACT#
LED0/LINK#
LED2/LINK100#
LED3/LINK1000#
SDP[7:6]
SDP[1:0]
Symbol
Symbol
Symbol
O
O
O
O
TS
TS
TS
Type
Type
O
O
O
O
Type
Flash Address Output. The Flash Address Output signals are used for a Flash or
Boot ROM device.
Flash Chip Select. The Flash Chip Select signal is used to enable the Flash or Boot
ROM device.
Flash Output Enable. The Flash Output Enable signal is used to enable the Flash
buffers.
Flash Write Enable Output. The Flash Write ENable Output signals are used for write
cycles.
Flash Data I/O. The Flash Data I/O signals are bi-directional and used for Flash data.
These signals include internal pull-up devices.
Flash Data I/O [1:0] / LAN Port Disable. These pins are inputs from the Flash
memory. Alternatively, they can be used to disable the LAN A or LAN B port from a
system Super I/O General (GP) port. (FL_DATA[1] corresponds to LAN B, and
FL_DATA[0], to LAN A.) They have internal pull-up devices. If the 82546GB is not using
Flash functionality, these pins should be connected to external pull-up resistors.
If the pins are used as LAN_DISABLE#, the device transitions to a low power state, and
the corresponding LAN port is disabled when its pin is sampled low on the rising edge
of PCI reset.
Software Defined Pin. The Software Defined Pins are reserved and programmable
with respect to input and output capability. These default to input signals upon power-
up but may be configured differently by the EEPROM. The upper four bits may be
mapped to the General Purpose Interrupt bits if they are configured as input signals.
Note: SDP5 is not included in the group of Software Defined Pins.
Activity. Programmable LED indication. Defaults to flash to indicate transmit or
receive activity.
Link. Programmable LED indication. Defaults to indicate link connectivity.
Link100. Programmable LED indication. Defaults to indicate link at 100 Mbps.
Link1000. Programmable LED indication. Defaults to indicate link at 1000 Mbps.
Name and Function
Name and Function
Name and Function
Networking Silicon — 82546GB
13