TXC-05802AIPQ Transwitch Corporation, TXC-05802AIPQ Datasheet - Page 37

• Manufacturer Part Number: TXC-05802AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-05802AIPQ

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature Classification: Industrial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / Rohs Status: Not Compliant

2. Status register at address 08H:
CRCF CRC-4 Error:
CRQOVF Control Receive Queue Overflow:
CRQCAV Control Receive Queue Cell Available:
INSOC Inlet Start of Cell:
CTSENT Control Cell Sent:
NOGRT No Grant:
OCOVF Outlet Cell Overflow:
Bit 7 (MSB)
CRCF
If the CRC-4 field H(3-0) of the CellBus Bus Routing Header in a cell received from the CellBus
bus does not match the calculated CRC-4, this bit is set to 1 (see Figure 5).
An overflow will occur, and this bit will be set to 1, when more than four cells try to accumulate
in the control receive queue.
When a control cell has been received from the CellBus bus and placed in the receive buffer
(addresses 60H-93H) this bit will be set to 1. This bit is cleared to 0 after the microprocessor
writes a 1 to CRQSENT.
In the ATM Layer Emulation UTOPIA 8-bit (PHYEN = High) and ATM Layer Emulation 16-Bit
(PHYEN = High) modes and the Back-to-Back mode, if CISOC is not present in the same
clock cycle that CICLAV is asserted, or if CISOC is asserted before the end of the current cell,
the INSOC bit is set to 1.
In the PHY Layer Emulation UTOPIA 8-bit (PHYEN = Low) and PHY Layer Emulation 16-Bit
(PHYEN = Low) modes, if CISOC is not present in the same clock cycle that CIENB is
asserted (after CICLAV has been asserted signaling the transfer of the first byte of the cell), or
if CISOC is asserted before the end of the current cell, the INSOC bit is set to 1. If the ONLINE
bit is set to 0 to disable cell acceptance at the cell inlet, arrival of a cell will cause INSOC to be
set to 1. In order to prevent generation of false interrupts, the interrupt-enable bit for INSOC
(INTEN4) should also be set to 0 when ONLINE is set to 0 in PHY layer emulation mode.
In ALI-25 mode, if RDVal is deasserted prematurely an INSOC error will occur.
When the microprocessor requests that a control cell be sent to the CellBus bus, this bit will be
set to 1 after the cell has been sent.
If the CUBIT- Pro device has requested a CellBus bus grant and has not received it after the
number of frames indicated by the TIME register (address 0FH), this bit will be set to 1.
In the single-queue mode an overflow will occur, and this bit will be set to 1, when more than
123 cells try to accumulate in the outlet queue.
In the split-queue mode this overflow will occur if any of the following events occurs:
a. More than 32 cells try to accumulate in the ABR queue
b. More than CBRLEN (address 10H) cells try to accumulate in the CBR queue
c. More than (89 minus CBRLEN) cells try to accumulate in the VBR queue
d. More than 2 cells try to accumulate in the control queue.
CRQOVF
Figure 29. CUBIT- Pro Status Register at Address 08H
CRQCAV
INSOC
- 37 -
CTSENT
NOGRT
RESERVED
Ed. 3, November 1999
Bit 0 (LSB)
TXC-05802
CUBIT- Pro
OCOVF
TXC-05802-MB