TXC-05802AIPQ Transwitch Corporation, TXC-05802AIPQ Datasheet - Page 79

• Manufacturer Part Number: TXC-05802AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-05802AIPQ

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature Classification: Industrial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / Rohs Status: Not Compliant

DEVICE MODE CONTROL BITS
Address
0C
0A
0B
5, 4, 3
7, 6
3, 2
7,6
3-0
Bit
5
4
1
0
5
4
7
6
2
1
0
CRQSENT Set to 1 by the microprocessor to indicate that a control cell has been read
TRHENA
GFCENA
LINEDIV
ONLINE
Symbol
CTRDY
CLKS1
CLKS0
P1, P0
IFECN
TRHIZ
UNI
QM
--
--
--
Set bus access priority of this CUBIT- Pro device. Possible values are:
high-priority, P1=1, P0=1; medium-priority, P1=1, P0=0; low-priority, P1=0,
P0=1; no request, P1=0, P0=0.
If = 1, UNI operation, VPI filled width = 8 bits. If = 0, NNI operation, VPI
filled width = 12 bits.
Enable insertion of Tandem Routing Header during address translation.
Reserved bits.
Set to 1 by microprocessor to indicate that a control cell is ready to be
sent. Cleared by CUBIT- Pro when cell has been sent.
from the CUBIT- Pro ’s control cell receive buffer. Cleared to 0 automatically
by CUBIT- Pro .
Reserved bits.
Clock source selection bit 1 for the cell inlet/outlet clock. This bit works in
conjunction with CLKS0. The coding followed is:
CLKS1, CLKS0 = 0,0: Cell interface clock = CellBus bus clock divided by 2
CLKS1, CLKS0 = 0,1: Cell interface clock = LCLOCK clock divided by 2
CLKS1, CLKS0 = 1,0: Cell interface clock = PCLK clock divided by 2
CLKS1, CLKS0 = 1,1: Reserved, do not use
Clock source selection bit 0 for the cell inlet/outlet clock. This bit works in
conjunction with CLKS1.
Cell inlet clock frequency control. Frequency will be equal to the frequency
of the selected clock source, divided by 2-to-the-power-LINEDIV.
Operational status. If = 1, the CUBIT- Pro is on-line and all functions are
operating. If = 0, the CUBIT- Pro is off-line. In off-line condition, no cells are
accepted from the cell inlet, the interface outputs are tri-stated, and only
control and loopback cells are accepted from the CellBus bus.
Translation RAM interface tri-state bit. When set to 1 and the ONLINE bit is
0, the translation RAM interface is put in Hi-Z mode.
Reserved bits.
Outlet cell queue structure. One single 123-cell queue if QM=0. Split
queue (Control Data, CBR, VBR, ABR) if QM = 1.
Enable insertion of the state of pins GFC(3-0) into the GFC field of outgo-
ing cells if = 1. State of GFC(3-0) is sampled on the rising edge of COCLK
that precedes the first byte of the ATM cell header (see Figure 47).
Enable insertion of FECN if = 1. The EFCI bit (middle bit of PT field) will be
set =1 if the CBR or VBR FIFO length equals or exceeds the congestion
limits, and IFECN = 1.
- 79 -
Description
LINEDIV
Ed. 3, November 1999
LINEDIV
LINEDIV
TXC-05802
CUBIT- Pro
TXC-05802-MB