L-ET1011C2-CI-D LSI, L-ET1011C2-CI-D Datasheet - Page 69

• Manufacturer Part Number: L-ET1011C2-CI-D
• Manufacturer: LSI

Specifications of L-ET1011C2-CI-D

• Number Of Receivers: 1
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / Rohs Status: Compliant

September 2007
LSI Corporation
Timing Specifications
RGMII 1000Base-T Transmit Timing
Trace Delay
Table 68. RGMII 1000Base-T Transmit Timing
1. This implies that PCB design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns will be added to
2. For 10Base-T and 100Base-TX, Tcyc scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
3. Duty cycle may be shrunk/stretched during speed changes or while transitioning to a received packet’s clock domain as long as minimum duty cycle is not
violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between.
the associated clock signal. To enable internal delay, see MII register 22 bits 2:0.
Symbol
TskewT
TskewR
Duty_G
Duty_T
AT TRANSMITTER
Tr/Tf
Tcyc
GTX_CLK (TXC)
(at transmitter)
TXD[8:5][3:0]
TXD[7:4][3:0]
TXC
AT TRANSMITTER
TX_EN
(TX_CTL)
TXC
GTX_CLK (TXC)
AT RECEIVER
(at receiver)
AT RECEIVER
TXD[8:5][3:0]
TXD[7:4][3:0]
TX_CLK
TX_CLK
TX_CTL
Data to Clock Output Skew (at transmitter)—Trace Delay
Data to Clock Input Skew (at receiver)—Trace Delay
Clock Cycle Duration
Duty Cycle for Gigabit
Duty Cycle for 10Base-T/100Base-TX
Rise/Fall Time (20%—80%)
Figure 17. RGMII 1000Base-T Transmit Timing—Trace Delay
(continued)
TXD[3:0]
TXD[3:0]
TXD[4]
TXEN
TX_EN
TXD[4]
2
3
Parameter
TXD[8:5]
TXD[7:4]
TXD[9]
TXERR
TXD[8:5]
TXD[7:4]
TX_ER
TXD[9]
3
TskewT
1
TskewR
TSKEWT
1
–500
Min
7.2
45
40
—
1
Gigabit Ethernet Transceiver
Typ
1.8
50
50
—
0
8
TSKEWR
Max
0.75
500
2.6
8.8
55
60
Unit
ps
ns
ns
%
%
ns
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