IS42S16320B-75ETL ISSI, Integrated Silicon Solution Inc, IS42S16320B-75ETL Datasheet - Page 49
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IS42S16320B-75ETL
Manufacturer Part Number
IS42S16320B-75ETL
Description
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet
1.IS42S16320B-75ETL.pdf
(62 pages)
Specifications of IS42S16320B-75ETL
Organization
32Mx16
Density
512Mb
Address Bus
15b
Access Time (max)
5.5ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
180mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S16320B-75ETL
Manufacturer:
ISSI
Quantity:
1 000
IS42S86400B, IS42/45S16320B
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/14/2010
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by programming
the write burst mode bit (M9) in the mode register to a logic
1. In this mode, all WRITE commands result in the access
of a single column location (burst of one), regardless of
the programmed burst length. READ commands access
columns according to the programmed burst length and
sequence, just as in the normal mode of operation (M9
= 0).
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another bank
while an access command with auto precharge enabled is
executing is not allowed by SDRAMs, unless the SDRAM
supports CONCURRENT AUTO PRECHARGE. ISSI
READ With Auto Precharge interrupted by a READ
READ With Auto Precharge interrupted by a WRITE
COMMAND
Internal States
COMMAND
Internal States
ADDRESS
ADDRESS
BANK m
BANK m
BANK n
BANK n
DQM
CLK
CLK
DQ
DQ
READ - AP
BANK n,
Page Active
BANK n
T0
T0
COL a
NOP
Page Active
CAS Latency - 3 (BANK n)
BANK n,
READ - AP
COL a
T1
BANK n
T1
NOP
Page Active
Page Active
READ with Burst of 4
READ with Burst of 4
CAS Latency - 3 (BANK n)
T2
T2
NOP
NOP
BANK n,
READ - AP
COL b
BANK m
T3
T3
NOP
D
OUT
a
CAS Latency - 3 (BANK m)
occurs are defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto precharge):
2. Interrupted by a WRITE (with or without auto precharge):
SDRAMs support CONCURRENT AUTO PRECHARGE.
Four cases where CONCURRENT AUTO PRECHARGE
Interrupt Burst, Precharge
A READ to bank m will interrupt a READ on bank n,
begin when the READ to bank m is registered.
A WRITE to bank m will interrupt a READ on bank n
when registered. DQM should be used three clocks prior
to the WRITE command to prevent bus contention. The
CAS latency later. The PRECHARGE to bank n will
PRECHARGE to bank n will begin when the WRITE to
bank m is registered.
WRITE - AP
BANK m,
BANK m
T4
T4
NOP
COL b
D
D
IN
t
OUT
RP - BANK n
READ with Burst of 4
b
a
Interrupt Burst, Precharge
WRITE with Burst of 4
T5
T5
D
NOP
NOP
D
IN
OUT
t
b+1
RP - BANK n
a+1
T6
T6
D
NOP
NOP
IN
D
OUT
b+2
b
DON'T CARE
DON'T CARE
Idle
T7
T7
D
NOP
D
NOP
IN
Write-Back
Precharge
OUT
b+3
t
t
RP - BANK m
DPL - BANK m
b+1
Idle
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