CY7C4255-25AC Cypress Semiconductor Corp, CY7C4255-25AC Datasheet - Page 15

• Manufacturer Part Number: CY7C4255-25AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4255-25AC

• Density: 128Kb
• Word Size: 18b
• Sync/async: Synchronous
• Expandable: Yes
• Package Type: TQFP
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-06004 Rev. *C
Architecture
The CY7C4256/65 consists of an array of 8K/16K words of 18
bits each (implemented by a dual-port array of SRAM cells), a
read pointer, a write pointer, control signals (RCLK, WCLK,
REN, WEN, RS), and flags (EF, PAE, HF, PAF, FF). The
CY7C4255/65 also includes the control signals WXI, RXI,
WXO, RXO for depth expansion.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition
signified by EF being LOW. All data outputs go LOW after the
falling edge of RS only if OE is asserted. In order for the FIFO
to reset to its default state, a falling edge must occur on RS
and the user must not read or write while RS is LOW.
FIFO Operation
When the WEN signal is active (LOW), data present on the
D
WCLK signal. Similarly, when the REN signal is active LOW,
data in the FIFO memory will be presented on the Q
outputs. New data will be presented on each rising edge of
RCLK while REN is active LOW and OE is LOW. REN must
set up t
must occur tENS before WCLK for it to be a valid write
function.
An output enable (OE) pin is provided to three-state the Q
outputs when OE is deasserted. When OE is enabled (LOW),
data in the output register will be available to the Q
after t
output data on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and under flow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q
even after additional reads occur.
Programming
The CY7C4255/65 devices contain two 14-bit offset registers.
Data present on D
the distance from Empty (Full) that the Almost Empty (Almost
Full) flags become active. If the user elects not to program the
FIFO’s flags, the default offset values are used (see Table 2).
When the Load LD pin is set LOW and WEN is set LOW, data
on the inputs D
the first LOW-to-HIGH transition of the Write Clock (WCLK).
When the LD pin and WEN are held LOW then data is written
into the Full offset register on the second LOW-to-HIGH
transition of the Write Clock (WCLK). The third transition of the
Write Clock (WCLK) again writes to the Empty offset register
(see Table 1). Writing all offset registers does not have to
occur at one time. One or two offset registers can be written
and then, by bringing the LD pin HIGH, the FIFO is returned to
Note:
36. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
0–17
OE
pins is written into the FIFO on each rising edge of the
ENS
. If devices are cascaded, the OE function will only
before RCLK for it to be a valid read function. WEN
0–13
0–13
is written into the Empty offset register on
during a program write will determine
0–17
0–17
outputs
outputs
0–17
0–17
normal read/write operation. When the LD pin is set LOW, and
WEN is LOW, the next offset register in sequence is written.
The contents of the offset registers can be read on the output
lines when the LD pin is set LOW and REN is set LOW; then,
data can be read on the LOW-to-HIGH transition of the Read
Clock (RCLK).
Table 1. Write Offset Register
Flag Operation
The CY7C4255/65 devices provide five flag pins to indicate
the condition of the FIFO contents. Empty and Full are
synchronous. PAE and PAF are synchronous if V
is tied to V
Full Flag
The Full Flag (FF) will go LOW when device is Full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN. FF is synchronized to WCLK, i.e., it is exclu-
sively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW,
regardless of the state of REN. EF is synchronized to RCLK,
i.e., it is exclusively updated by each rising edge of RCLK.
Programmable Almost Empty/Almost Full Flag
The CY7C4255/65 features programmable Almost Empty and
Almost Full Flags. Each flag can be programmed (described
in the Programming section) a specific distance from the corre-
sponding boundary flags (Empty or Full). When the FIFO
contains the number of words or fewer for which the flags have
been programmed, the PAF or PAE will be asserted, signifying
that the FIFO is either Almost Full or Almost Empty. See
Table 2 for a description of programmable flags.
When the SMODE pin is tied LOW, the PAF flag signal
transition is caused by the rising edge of the write clock and
the PAE flag transition is caused by the rising edge of the read
clock.
LD
0
0
1
1
WEN
0
1
0
1
SS
.
WCLK
[36]
Writing to offset registers:
Empty Offset
Full Offset
No Operation
Write Into FIFO
No Operation
Selection
CY7C4255
CY7C4265
Page 15 of 22
CC
/SMODE
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