CY7C4255-10AC Cypress Semiconductor Corp, CY7C4255-10AC Datasheet
CY7C4255-10AC
Specifications of CY7C4255-10AC
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CY7C4255-10AC Summary of contents
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... FIFO on each cycle. The output port is controlled in a similar manner by a free-running Read Clock (RCLK) and a Read Enable pin (REN). In addition, the CY7C4255/65 have an Output Enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications ...
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... Functional Description (continued) The CY7C4255/65 provides five status pins. These pins are decod determine one of five states: Empty, Almost Empty, Half Full, Almost Full, and Full. The Half Full flag shares the WXO pin. This flag is valid in the stand-alone and width-expansion configurations. In ...
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... HIGH, the FIFO’s outputs are in High Z (high-impedance) state. I Dual-Mode Pin: Asynchronous Almost Empty/Almost Full flags – tied to V Synchronous Almost Empty/Almost Full flags – tied to V (Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.) CY7C4255 CY7C4265 Function /SMODE is tied CC /SMODE is tied to V ...
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... V < Com’l 45 Ind 50 Com’l 10 Ind 15 Test Conditions T = 25° MHz 5.0V CC CY7C4255 CY7C4265 [2] Ambient Temperature 0°C to +70°C [3] –40°C to +85°C 7C42X5–15 7C42X5–25 7C42X5– 35 Min. Max. Min. Max. Min. 2.4 2.4 2.4 0.4 0.4 2 ...
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... Equivalent to: THÉ VENIN EQUIVALENT OUTPUT 7C42X5-10 Min. Max. Min. Max. Min. Max. 100 4.5 4.5 3 0 [12 [13 [13] 12 /SMODE tied /SMODE tied [14] 12 /SMODE tied OHZ . PAF(E) CY7C4255 CY7C4265 ALL INPUT PULSES 90% 90% 10% 10 410 1.91V 7C42X5-15 7C42X5-25 7C42X5-35 Min. 66 ...
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... Skew Time between Read Clock and Write SKEW3 Clock for Programmable Almost Empty and Pro- grammable Almost Full Flags (Synchronous Mode only) Document #: 38-06004 Rev. *A 7C42X5-10 Min. Max. Min. Max. Min. Max. 8 /SMODE tied 4 CY7C4255 CY7C4265 7C42X5-15 7C42X5-25 7C42X5-35 Min. Max 6 ...
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... ENH NO OPERATION t REF [16] t SKEW2 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 CY7C4255 CY7C4265 ENH NO OPERATION t WFF t REF VALID DATA t OHZ 4255–6 4255–7 ...
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... The first word is available the cycle after EF goes HIGH, always. Document #: 38-06004 Rev RSF t RSF t RSF D 1 [19] t FRL t SKEW2 t REF t OLZ t OE (maximum When t < minimum specification, t CLK SKEW2 SKEW2 CY7C4255 CY7C4265 t RSR [18] OE=1 OE [19 (maximum) = either 2 FRL CLK SKEW2 4255– 4255– ...
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... WEN RCLK t ENS REN LOW OE DATA IN OUTPUT REGISTER Q – Document #: 38-06004 Rev. *A [18 REF REF DATA WRITE t WFF t ENH t A DATA READ CY7C4255 CY7C4265 ENH ENS [18] t FRL t t SKEW2 D0 NO WRITE [15] t SKEW1 t t WFF WFF t ENH t ENS t A NEXT DATA READ REF 4255– ...
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... PAE is offset = n. Number of data words into FIFO already = n. Document #: 38-06004 Rev CLKL CLKH t t ENS ENH CLKL CLKH t t ENS ENH t PAE CY7C4255 CY7C4265 HALF FULL + 1 OR MORE HALF FULLOR LESS ENS WORDS n WORDS IN FIFO IN FIFO t PAE t ENS 4255–12 4255–13 Page ...
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... If a read is preformed on this rising edge of the read clock, there will be Empty + (n 1) words in the FIFO when PAE goes LOW. 25. PAF offset = m. Number of data words written into FIFO already = 8192 26. PAF is offset = m. 27. 8192 m words in CY7C4255 and 16384 – m words in CY7C4265. 28. 8192 ( words in CY7C4255 and 16384 – CY7C4265. ...
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... PAF ENS ENH t CLKL t ENH t DH PAE OFFSET PAF OFFSET (m 1) words of the FIFO when PAF goes LOW. , then PAF may not change state until the next WCLK rising edge. CY7C4255 CY7C4265 FULL– M WORDS [27] IN FIFO t [31] PAF synch t SKEW3 ...
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... WCLK Notes: 32. Write to Last Physical Location. 33. Read from Last Physical Location. Document #: 38-06004 Rev CLKL t ENH t A UNKNOWN PAE OFFSET t CLKH Note Note CLKH Note XIS CY7C4255 CY7C4265 PAF OFFSET PAE OFFSET 4255–18 4255–19 4255–20 4255–21 Page ...
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... The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t 36. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t Document #: 38-06004 Rev XIS t PRT t RTR RTR to update these flags. RTR CY7C4255 CY7C4265 4255–22 4255–23 . Page ...
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... SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, HF, PAF, FF). The CY7C4255/65 also includes the control signals WXI, RXI, WXO, RXO for depth expansion. Resetting the FIFO Upon power-up, the FIFO must be reset with a Reset (RS) cycle ...
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... Notes: 38 Empty Offset (Default Values: CY7C4255/CY7C4265 n = 127). 39 Full Offset (Default Values: CY7C4255/CY7C4265 n = 127). Document #: 38-06004 Rev. *A nal read pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and t after the retransmit pulse. With every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer ...
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... Width Expansion Configuration The CY7C4255/65 can be expanded in width to provide word widths greater than 18 in increments of 18. During width ex- pansion mode all control line inputs are common and all flags are available. Empty (Full) flags should be created by ANDing RESET (RS) DATA IN ( WRITE CLOCK (WCLK) ...
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... Depth Expansion Configuration (with Programmable Flags) The CY7C4255/65 can easily be adapted to applications re- quiring more than 8192/16384 words of buffering. Figure 2 shows Depth Expansion using three CY7C42X5s. Maximum depth is limited only by signal loading. Follow these steps: 1. The first device must be designated by grounding the First Load (FL) control input ...
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... NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.20 1.10 1. 3. MHz 0.80 55.00 5.00 65.00 AMBIENT TEMPERATURE ( C) CY7C4255 CY7C4265 vs. AMBIENT 5.0V CC 5.00 65.00 125.00 AMBIENT TEMPERATURE( C) NORMALIZED SUPPLY CURRENT vs. FREQUENCY 1.75 1.50 1.25 1. 0.50 125.00 20 ...
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... Ordering Information 8Kx18 Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4255–10AC CY7C4255-10ASC 15 CY7C4255–15AC CY7C4255-15ASC 25 CY7C4255–25AC 16Kx18 Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4265–10AC CY7C4265-10ASC CY7C4265–10AI 15 CY7C4265–15AC CY7C4265-15ASC 25 CY7C4265–25AC CY7C4265-25ASC Package Diagrams 64-Pin Thin Plastic Quad Flat Pack ( 1.4 mm) A64 Document #: 38-06004 Rev ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C4255 CY7C4265 ...
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... Document Title: CY7C4255, CY7C4265 8K/16K X 18 Deep Sync FIFOs Document Number: 38-06004 Issue REV. ECN NO. Date ** 106465 07/11/01 *A 122257 12/26/02 Document #: 38-06004 Rev. *A Orig. of Change SZV Change from Spec Number: 38-00468 to 38-06004 RBI Power up requirements added to Maximum Ratings Information CY7C4255 CY7C4265 ...