JD54LS164BCA National Semiconductor, JD54LS164BCA Datasheet - Page 63

• Manufacturer Part Number: JD54LS164BCA
• Manufacturer: National Semiconductor

Specifications of JD54LS164BCA

• Lead Free Status / Rohs Status: Not Compliant

FOOTNOTES:
A. Apply input pulse:
B. V
C. V
D. Test numbers 59 through 111 shall be run in sequence.
E. Output voltages shall be either: (1) H 2.5 V minimum and L 0.4 V maximum when using a high speed checker double comparator: (2) H 1.5 V and L <1.5 V when using a high
F. f
G. 3.0 V minimum/5.0 V maximum.
J. At the manufacturer's option, the following alternate procedure may be used to guarantee f
1/ This pulse must occur after the clear pulse.
2/ I
speed checker single comparator.
be one-half of the clock input frequency and the A
volts.
times (after reset) at f
the data input, to guarantee both LH and HL transition of the output pulse.
MAX
IL
IN
IN
limits (mA) min/max values for circuits shown:
= 2.5 V.
= 0.4 V.
Parameter
minimum limit specified is the frequency of the clock input pulse. The output frequency shall be one-half of the clock input frequency. The input frequency on the A
I
I
I
I
IL1
IL2
IL3
IL4
S/R, A
C
Terminal
IN
, D
S
MAX
CLR
CLK
0
, S
IN
IN
and looking for the Q
, S/L
, B
1
IN
2.5 V minimum/5.5 V maximum
0 V
-.16/-.4
A
"
"
"
-.11/-.35
-.11/-.35
-.03/-.3
-.03/-.3
D
output to toggle within three periods (3 x 1/ f
B
IN
shall be shifted such that the A
-.20/-.44
-.16/-.4
C
"
"
-.12/-.35
-.12/-.36
-.12/-.36
-.16/-.4
D
IN
-.105/-.345
-.12/-.36
-.12/-.36
-.12/-.36
and
E
MAX
MAX
are coincident with the clock
. Serial mode - f
) plus allowed propagation delay. Two tests are performed, depending on the state of
-.12/-.36
F
"
"
"
MAX
-.15/-.38
-.16/-.4
G
for the serial mode shall be guaranteed by clocking the device four
"
"
. Rise and fall times
6 ns. Input peak voltage 3 to 5
IN
data shall