JD54LS164BCA National Semiconductor, JD54LS164BCA Datasheet - Page 72

• Manufacturer Part Number: JD54LS164BCA
• Manufacturer: National Semiconductor

Specifications of JD54LS164BCA

• Lead Free Status / Rohs Status: Not Compliant

Tc = 25 C
Subgroup
Notes:
A. Apply input pulse:
B. V
C. V
D. Tests numbers 48 through 79 shall be run in sequence.
E. Output voltages shall be either: (1) H 2.5 minimum and L 0.4 V maximum when using a high speed
F. f
G. 3.0 V minimum/5.0 V maximum.
J. At the manufacturer's option, the following alternate procedures may be used to guarantee f
10
11
The output frequency shall be one-half of the input clock frequency. The input frequency on the
serial input shall be one-half of the clock input frequency and the input shall be shifted such that
the input
voltage 3 to 5 volts.
checker double comparator; (2) H 1.5 V and L 1.5 V when using a high speed checker single
comparator.
MAX
IN
IN
a. Parallel mode. f
b. Serial mode. f
= 0.4 V.
= 2.5 V.
f
t
t
Same tests, terminal conditions as subgroup 10 except T
minimum limit specified is the frequency of the clock input pulse.
See F,J
MAX
PLH1
PHL1
Symbol
delay measurements with the clock pulse width at 1/2 x 1/f
constraints on the clock pulse, the inputs are set to the worst-case condition for the
t
tested. The five tests to justify each JAN f
possible input/output combinations. A failing limit or nontoggle will indicate that the device
fails to function at f
allowed limit .
set-up
(after reset) at f
1/f
data input, to guarantee both LH and HL transition of the output pulse.
MAX
and t
) plus allowed propagation delay. Two tests are performed, depending on the state of
and
MIL-STD-
method
(Fig. 6)
(Fig. 6)
(Fig. 6)
hold
3003
3003
3003
883
↓
requirements. Both positive and negative clock pulse widths shall be
are coincident with the clock
MAX
MAX
MAX
MAX
for the serial mode shall be guaranteed by clocking the device four times
and looking for the Q
Cases 2, X
for the parallel mode shall be guaranteed by performing propagation
101 to 105
106 to 113
114 to 121
A,B,C,D
Test no.
Cases
and/or the propagation delay from input to output has exceeded the
Same tests and terminal conditions as for subgroup 9.
Serial
2
1
2.5 V minimum/5.5 V maximum
0 V
D
Terminal conditions (pins not designated may be high
MAX
output to toggle within three periods (3 x
A
2
3
IN
. Rise and fall times
requirement shall be used to test all
TABLE III. Group A inspection for device type 03 - Continued.
C
= -55 C.
B
3
4
IN
MAX
C
4
6
. In addition to the
IN
D
5
8
ns. Input peak
IN
Mode
6
9
GND
MAX
10
7
:
CLK
12
8
2.0 V or low
2
CLK
13
9
1
0.7 V or open).
QD
10
14
QC
11
16
QB
12
18
QA
13
19
V
14
20
CC
Measured
terminal
Min
20
5
5
Limits
Max
---
48
56
MHz
Unit
ns
ns