EVAL-AD7274CB Analog Devices Inc, EVAL-AD7274CB Datasheet - Page 21

• Manufacturer Part Number: EVAL-AD7274CB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7274CB

• Lead Free Status / Rohs Status: Not Compliant

SERIAL INTERFACE
Figure 36 through Figure 38 show the detailed timing diagrams
for serial interfacing to the AD7274 and AD7273, respectively.
The serial clock provides the conversion clock and controls the
transfer of information from the AD7273/AD7274 during
conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
and takes the bus out of three-state. The analog input is sampled
and the conversion is initiated at this point.
For the AD7274, the conversion requires completing 14 SCLK
cycles. Once 13 SCLK falling edges have elapsed, the track-and-
hold goes back into track mode on the next SCLK rising edge,
as shown in Figure 36 at Point B. If the rising edge of CS occurs
before 14 SCLKs have elapsed, the conversion is terminated and
the SDATA line goes back into three-state. If 16 SCLKs are
considered in the cycle, the last two bits are zeros and SDATA
returns to three-state on the 16
Figure 37.
For the AD7273, the conversion requires completing 12 SCLK
cycles. Once 11 SCLK falling edges elapse, the track-and-hold
goes back into track mode on the next SCLK rising edge, as
shown in Figure 38 at Point B. If the rising edge of CS occurs
before 12 SCLKs elapse, the conversion is terminated and the
SDATA line goes back into three-state. If 16 SCLKs are
considered in the cycle, the AD7273 clocks out four trailing
zeros for the last four bits and SDATA returns to three-state on
the 16
th
SCLK falling edge, as shown in Figure 38.
SDATA
SCLK
CS
THREE-
STATE
t
2
Z
TWO LEADING
1
t
ZEROS
3
ZERO
th
SCLK falling edge, as shown in
2
DB11
Figure 36. AD7274 Serial Interface Timing Diagram 14 SCLK Cycle
3
t
DB10
CONVERT
4
DB9
t
t
4
6
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1/THROUGHPUT
5
If the user considers a 14-SCLK cycle serial interface for the
AD7273/AD7274, CS must be brought high after the 14
falling edge. Then the last two trailing zeros are ignored, and
SDATA goes back into three-state. In this case, the 3 MSPS
throughput can be achieved by using a 48 MHz clock frequency.
CS going low clocks out the first leading zero to be read by the
microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges, beginning with the second
leading zero. Therefore, the first falling clock edge on the serial
clock provides the first leading zero and clocks out the second
leading zero. The final bit in the data transfer is valid on the 16
falling edge, because it is clocked out on the previous (15
falling edge.
In applications with a slower SCLK, it is possible to read data on
each SCLK rising edge. In such cases, the first falling edge of
SCLK clocks out the second leading zero and can be read on the
first rising edge. However, the first leading zero clocked out
when CS goes low is missed if read within the first falling edge.
The 15
read on the 15
If CS goes low just after one SCLK falling edge elapses, CS
clocks out the first leading zero and can be read on the SCLK
rising edge. The next SCLK falling edge clocks out the second
leading zero and can be read on the following rising edge.
t
DB1
7
th
13
t
5
falling edge of SCLK clocks out the last bit and can be
DB0
B
th
rising SCLK edge.
14
t
9
THREE-STATE
t
QUIET
t
1
AD7273/AD7274
th
th
SCLK
)
th