KU82596CA33 S Z717 Intel, KU82596CA33 S Z717 Datasheet - Page 10

• Manufacturer Part Number: KU82596CA33 S Z717
• Manufacturer: Intel

Specifications of KU82596CA33 S Z717

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

PIN DESCRIPTIONS
BS16
HOLD
HLDA
BREQ
PORT
RESET
LE BE
CA
INT INT
Symbol
Pin No
PQFP
129
123
118
115
119
125
69
65
3
(Continued)
Type
O
O
I
I
I
I
I
I
I
Do not connect HLDA to V
BUS SIZE This signal allows the 82596CA to work with either 16- or
32-bit bytes Inserting BS16 low causes the 82596 to perform two 16-
bit memory accesses when transferring 32-bit data In little endian
mode the D15 – D0 lines are driven when BS16 is inserted in Big
Endian mode the D31 – D16 lines are driven
HOLD The HOLD signal is active high the 82596 uses it to request
local bus mastership In normal operation HOLD goes inactive before
HLDA The 82596 can be forced off the bus by deasserting HLDA or if
the bus throttle timers expire
HOLD ACKNOWLEDGE The HLDA signal is active high it indicates
that bus mastership has been given to the 82596 HLDA is internally
synchronized after HOLD is detected low the CPU drives HLDA low
to give the 82596 permanent access to the bus should connect HLDA
to HOLD If HLDA goes inactive before HOLD the 82596 will release
the bus (by deasserting HOLD) within a maximum of within a specified
number of bus cycles as specified in the 82596 User’s Manual
BUS REQUEST This signal when configured to an externally
activated mode is used to trigger the bus throttle timers
PORT When this signal is received the 82596 latches the data on the
data bus into an internal 32-bit register When the CPU is asserting this
signal it can write into the 82596 (via the data bus) This pin must be
activated twice during all CPU Port access commands
RESET This active high internally synchronized signal causes the
82596 to terminate current activity The signal must be high for at least
five system clock cycles After five system clock cycles and four TxC
clock cycles the 82596 will execute a Reset when it receives a high
RESET signal When RESET returns to low the 82596 waits for the
first CA signal and then begins the initialization sequence
LITTLE ENDIAN BIG ENDIAN This dual-function pin is used to
select byte ordering When LE BE is high little endian byte ordering is
used when low big endian byte ordering is used for data in frames
(bytes) and for control (SCB RFD CBL etc)
CHANNEL ATTENTION The CPU uses this pin to force the 82596 to
begin executing memory resident Command blocks The CA signal is
internally synchronized The signal must be high for at least one
system clock It is latched internally on the high to low edge and then
detected by the 82596
The first CA after a Reset forces the 82596 into the initialization
sequence beginning at location 00FFFFF6h or an SCP address written
to the 82596 using CPU Port access All subsequent CA signals cause
the 82596 to begin executing new command sequences from the SCB
INTERRUPT A high signal on this pin notifies the CPU that the 82596
is requesting an interrupt This signal is an edge triggered interrupt
signal and can be configured to be active high or low
Name and Function
CC
it will cause a deadlock A user wanting
NOTE
82596CA
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