PRIXP425ABB 885157 Intel, PRIXP425ABB 885157 Datasheet - Page 11
PRIXP425ABB 885157
Manufacturer Part Number
PRIXP425ABB 885157
Description
Manufacturer
Intel
Datasheet
1.PRIXP425ABB_885157.pdf
(96 pages)
Specifications of PRIXP425ABB 885157
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Introduction—Intel
1.4
1.5
December 2007
Document Number: 252817-008US
Overview
The IXP42X product line and IXC1100 control plane processors are multi-function
processors and incorporate many advanced architecture features, including an
industry-standard, 32-bit PCI controller, UART, PC133 SDRAM memory controller,
interrupt controller, Intel XScale
5TE instruction set architecture (ISA), USB (device only), UTOPIA-2, GPIO, 133-MHz
internal bus, AHB bridges, timers, 8-Kbyte Queue Manager, PMU, Network Processor
Engines (NPEs), and industry-standard Media Independent Interfaces (MII).
With the highly integrated solution and rich feature set, the processors deliver high
performance system-on-chip and helps to reduce the overall cost of system
implementations.
The processors can operate at a variety of frequencies, allowing systems designers to
trade off performance for lower power consumption. The Intel XScale
Microarchitecture and the internal components are clocked from an internal PLL. The
internal and external interfaces use a 66/133-MHz, 32-bit data bus; a 32-bit address
bus; and control signals that enable the interface between the Intel XScale
Microarchitecture and peripheral logic to optimize performance.
Key Features
• Intel XScale
• PCI interface
®
IXP42X product line and IXC1100 control plane processors
— High-performance processor based on Intel XScale
— Seven/eight-stage Intel
— Management unit
— Clock speeds:
— ARM* Version 5TE Compliant
— Intel
— Debug unit. Accessible through JTAG port
— 32-bit interface
— Selectable clock
— PCI Local Bus Specification, Rev. 2.2 compatible
— PCI arbiter supporting up to four external PCI devices (four REQ/GNT pairs)
— Host/option capable
— Master/target capable
• 32-entry, data memory management unit
• 32-entry, instruction memory management unit
• 32-Kbyte, 32-way, set associative instruction cache
• 32-Kbyte, 32-way, set associative data cache
• 2 Kbyte, two-way, set associative mini-data cache
• 128-entry, branch target buffer
• Eight-entry write buffer
• Four-entry fill and pend buffers
• 266 MHz
• 400 MHz
• 533 MHz
Multiply-accumulate coprocessor
• 33-MHz clock output derived from either GPIO14 or GPIO15
• 0- to 66-MHz clock input
®
Media Processing Technology
®
Processor (compliant with Intel
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
®
®
Super-Pipelined RISC Technology
Microarchitecture compliant with the ARM* Version
®
StrongARM
®
technology
*
architecture)
Hardware Design Guidelines
®
®
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