RPIXP2800BB Intel, RPIXP2800BB Datasheet - Page 62
RPIXP2800BB
Manufacturer Part Number
RPIXP2800BB
Description
Manufacturer
Intel
Datasheet
1.RPIXP2800BB.pdf
(154 pages)
Specifications of RPIXP2800BB
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
RPIXP2800BB
Manufacturer:
MXIC
Quantity:
834
Part Number:
RPIXP2800BB
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
IXP28XX Network Processor
QDR SRAM
4.4.2
Table 17.
4.4.3
Table 18.
62
QDRn_A[23:0]
QDRn_K_H[1:0]
QDRn_K_L[1:0]
QDRn_K_H[1:0]
QDRn_K_L[1:0]
QDRn_C_H[1:0]
QDRn_C_L[1:0]
QDRn_C_H[1:0]
QDRn_C_L[1:0]
IXP28XX Signals
Address
K Clocks
C Clocks
D (Write)
Q (Read)
Control
WPE/RPE
Control
BWE
Signal Groups
The QDR interface has six groups of signals. These are the K-Clocks, the C-Clocks, Address,
Data-OUT or WRITE, Data-IN or READ, and Control. The Control group has three signals, the
WRITE PORT ENABLE Active Low, the READ PORT ENABLE Active Low, and the BYTE
WRITE ENABLE Active Low. The Address, Data-OUT, Data-IN, and the BYTE WRITE
ENABLE are all Double Data Rate, while the WRITE PORT ENABLE and the READ PORT
ENABLE are single data rate.
An overall summary of these signal groups with topology details is depicted in
An Overview of QDR signal groups
QDR Signal Mapping
QDR SRAM Signal Mapping (Sheet 1 of 2)
Signals
A[23..0]
K0, K0#
–
C0, C0#
–
Top SRAM 1
(2Mx9)
T-Topology
Point-to-Point
Point-to-Point
T-Topology/Daisy-
Chain
T-Topology
T-Topology
T-Topology/Daisy-
Chain
Topology
A[23..0]
K0, K0#
–
C0, C0#
–
Bottom SRAM 2
(2Mx9)
30 Ohm
Driver
50 Ohm
Driver
50 Ohm
Driver
50 Ohm
Driver
SRAM
30 Ohm
Driver
30 Ohm
Driver
Driver
–
PU50Ω
–
On-die at
IXP28XX
Receiver
–
Termination
V
TT
=0.75 V
34 Ohm
50 Ohm
50 Ohm
50 Ohm
50 Ohm
34 Ohm
34 Ohm
Impedance
Trace
A[23..0]
–
K1, K1#
–
C1, C1#
Top SRAM 3
(2Mx9)
4 SRAMs
2 SRAMs
2 SRAMs
2 SRAMs
2 SRAMs
2 SRAMs
2 SRAMs
Loads
No of
Bottom SRAM 4
A[23..0]
–
K1, K1#
–
C1, C1#
(2Mx9)
Hardware Design Guide
35 Ohm
50 Ohm
50 Ohm
50 Ohm
50 Ohm
35 Ohm
35 Ohm
Termination
Table 17
PU35Ω Center
Termination at
T-junction
–
PU50Ω
On-die at
IXP28XX
Receiver
–
Center @ T
Point
@SRAM Input
On Die @
IXP2800 (CIN
Inputs)
@ T Point
On Die @
IXP2800
@ T Point
@ T Point
Termination
V
Termination
TT
Position
below.
=0.75 V
1