KU82596CA33 S N222 Intel, KU82596CA33 S N222 Datasheet - Page 64

• Manufacturer Part Number: KU82596CA33 S N222
• Manufacturer: Intel

Specifications of KU82596CA33 S N222

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

AC Characteristics
82596CA C-STEP INPUT OUTPUT SYSTEM TIMINGS
C
All timing requirements are given in nanoseconds
NOTES
your local Intel representative
1 RESET HLDA and CA are internally synchronized This timing is to guarantee recognition at next clock for RESET HLDA
and CA
2 All set-up hold and delay timings are at maximum frequency specification Fmax and must be derated according to the
3 CA pulse width need only be 1 T1 wide if the set up and hold times are met BREQ must meet setup and hold times and
need only be 1 T1 wide
TRANSMIT RECEIVE CLOCK PARAMETERS
Timings shown are for the 82596CA C-stepping For information regarding timings for the 82596CA A1 or B-step contact
L
following equation for operation at lower frequencies
Tderated
where
Tderate
Fmax
Fopr
T
This calculation only provides a rough estimate for derating the frequency For more detailed information contact your
Intel Sales Office for the data sheet supplement
on all outputs is 50 pF unless otherwise specified
e
Symbol
T36
T38
T39
T40
T41
T42
T43
T44
T45
T46
T47
T48
Symbol
T22a
T23
T24
T25
T26
T27
T28
T29
T30
T31
T32
Specification at maximum frequency
e
e
Actual operating frequency
e
Maximum operating frequency
e
Specifies the value to derate the specification
(Fmax Fopr)
TxC Cycle
TxC Rise Time
TxC Fall Time
TxC High Time
TxC Low Time
TxD Rise Time
TxD Fall Time
TxD Transition
TxC Low to TxD Valid
TxC Low to TxD Transition
TxC High to TxD Transition
TxC Low to TxD High (At End of Transition)
HLDA Hold Time
RESET Setup Time
RESET Hold Time
INT INT Valid Delay
CA and BREQ PORT Pulse Width
D0 – D31 CPU PORT Access Setup Time
D0 – D31 CPU PORT Access Hold Time
PORT Setup Time
PORT Hold Time
BOFF Setup Time
BOFF Hold Time
c
(Continued)
T
Parameter
Parameter
Min
2T1
4 5
10
3
9
3
1
6
7
3
3
Min
50
19
18
20
33 MHz
20 MHz
Max
Max
20
10
10
25
25
25
25
5
5
Notes
82596CA
1 2 3
Notes
1 2
1 2
1 2
1 3
1 3
1 3
2 4
4 6
2 4
2 4
2
2
2
2
2
2
1
1
4
4
4
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