CY7C53120E4-40SI Cypress Semiconductor Corp, CY7C53120E4-40SI Datasheet

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CY7C53120E4-40SI

Manufacturer Part Number
CY7C53120E4-40SI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C53120E4-40SI

Core Operating Frequency
40MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Not Compliant

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Cypress Semiconductor Corporation
Document #: 38-10001 Rev. *F
Features
Notes
1. Rare combinations of wake-up events occurring during the go to sleep sequence could produce unexpected sleep behavior. See the
2. Maximum Junction Temperature is 105°C. T
Three 8-bit pipelined processors for concurrent processing
of application code and network traffic
11-pin I/O port programmable in 34 modes for fast application
program development
Two 16-bit timer/counters for measuring and generating I/O
device waveforms
5-pin communication port that supports direct connect and
network transceiver interfaces
Programmable pull ups on IO4–IO7 and 20 mA sink current
on IO0–IO3
Unique 48-bit ID number in every device to facilitate network
installation and management
Low operating current; sleep mode operation for reduced
current consumption
0.35 μm Flash process technology
5.0V operation
Logic Block Diagram
Manual
for more details.
Control Processor
Media Access
(CY7C53120)
Application
[1]
Processor
Processor
2 KB RAM
Network
Flash
ROM
Junction
= T
198 Champion Court
Ambient
+ V•I•
θ
Address Bus
JA
. 32-pin SOIC
Data Bus
Internal
Internal
(0:15)
(0:7)
Neuron Chip Network Processor
On-chip LVD circuit to prevent nonvolatile memory corruption
during voltage drops
2,048 bytes of SRAM for buffering network data, system, and
application data storage
512 bytes (CY7C53150), 2048 bytes (CY7C53120E2), 4096
bytes (CY7C53120E4) of Flash memory with on-chip charge
pump for flexible storage of configuration data and appli-
cation code
Addresses up to 58 KB of external memory (CY7C53150)
10 KB (CY7C53120E2), 12 KB (CY7C53120E4) of ROM
containing LonTalk network protocol firmware
Maximum input clock operation of 20 MHz (CY7C53150),
10 MHz (CY7C53120E2), 40 MHz (CY7C53120E4) over a
–40°C to 85°C
64-pin TQFP package (CY7C53150)
32-pin SOIC or 44-pin TQFP package (CY7C53120)
θ
JA
= 51C/W. 44-pin TQFP
San Jose
[2]
temperature range
Communications
,
CY7C53150, CY7C53120
CA 95134-1709
Clock, and
Counters
Oscillator,
I/O Block
2 Timer/
Control
θ
Port
JA
= 43C/W. 64-pin TQFP
Revised November 20, 2009
External
Address/Data Bus
(CY7C53150)
Neuron Technical Reference
CP4
CP0
IO10
IO0
CLK1
CLK2
SERVICE
RESET
θ
JA
408-943-2600
= 44C/W.
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CY7C53120E4-40SI Summary of contents

Page 1

... Addresses external memory (CY7C53150) ■ (CY7C53120E2 (CY7C53120E4) of ROM containing LonTalk network protocol firmware ■ Maximum input clock operation of 20 MHz (CY7C53150), 10 MHz (CY7C53120E2), 40 MHz (CY7C53120E4) over a –40°C to 85°C ■ 64-pin TQFP package (CY7C53150) ■ 32-pin SOIC or 44-pin TQFP package (CY7C53120) ...

Page 2

Contents Functional Description........................................................ 3 Pin Configurations .............................................................. 3 Pin Descriptions .................................................................. 5 Memory Usage ..................................................................... 6 Flash Memory Retention and Endurance.......................... 6 40 MHz 3120 Operation ....................................................... 6 Low Voltage Inhibit Operation............................................ 6 Communications Port ......................................................... 6 Programmable Hysteresis Values ...

Page 3

... Document #: 38-10001 Rev. *F Services at every layer of the OSI networking reference model are implemented in the LonTalk firmware based protocol stored in 10-KB ROM (CY7C53120E2), 12-KB ROM (CY7C53120E4), or off-chip memory (CY7C53150). The firmware also contains 34 preprogrammed I/O drivers, greatly simplifying application programming. The application program is stored in the Flash memory (CY7C53120) and/or off-chip memory (CY7C53150), and may be updated by downloading over the network ...

Page 4

RESET IO4 3 30 IO5 IO3 4 29 IO6 IO2 5 28 IO7 IO1 6 27 IO8 IO0 7 26 IO9 SERVICE IO10 ...

Page 5

Pin Descriptions Pin Name I/O CLK1 Input Oscillator connection or external clock input. CLK2 Output Oscillator connection. Leave open when external clock is input to CLK1. Maximum of one external load. RESET I/O (Built-In Reset pin (active LOW). Note The ...

Page 6

... In addition, system firmware version 13.1 or higher is able to aggregate writes to eight successive address locations into a single write for CY7C53120E4 devices. For example code is downloaded over the network, the firmware would execute only 512 writes rather than 4,096. ...

Page 7

Programmable Hysteresis Values (Expressed as differential peak-to-peak voltages in terms of V [6] Hysteresis V Min V Typ hys hys 0 0.019 V 0.027 0.040 V 0.054 0.061 V 0.081 0.081 ...

Page 8

... LVI Trip Point ( Part Number CY7C53120E2, CY7C53120E4, and CY7C53150 Notes 11. Standard outputs are IO4–IO10, CP0, CP1, and CP4. (RESET is an open drain input/output. CLK2 must have < load.) For CY7C53150, standard outputs also include A0–A15, D0–D7, E, and R/W. 12. IO4–IO7 and SERVICE have configurable pull ups. RESET has a permanent pull up. ...

Page 9

External Memory Interface Timing — CY7C53150, V Parameter Description t Memory Cycle Time (System Clock Period) cyc [16] PW Pulse Width, E High EH [16] PW Pulse Width, E Low EL t Delay, E High to Address Valid AD t ...

Page 10

Figure 6. Drive Levels and Test Point Levels for Timing Specifications Unless Otherwise Specified DRIVE TO 2.4V DRIVE TO 0.4V A — Signal valid-to-signal valid specification (maximum or minimum) B — Signal valid-to-signal invalid specification (maximum or minimum) Figure 7. ...

Page 11

... All parts contain SRAM. 24. CY7C53120E2 firmware is bit-for-bit identical with Motorola MC143120E2 firmware. 25. CY7C53150 may be used with 20-MHz input clock only if the firmware in external memory is version 13 or later. 26. CY7C53120E4 requires upgraded LonBuilder® and NodeBuilder® software. Document #: 38-10001 Rev trip - Max Input ...

Page 12

Package Diagrams Figure 11. 44-Pin Thin Plastic Quad Flat Pack A44 12.00±0.25 SQ 10.00±0. SEATING PLANE 1.60 MAX. 0.10 0.20 MAX. Document #: 38-10001 Rev 0.37±0.05 STAND-OFF 0.05 MIN. 0.15 MAX. 0.80 ...

Page 13

Package Diagrams (continued) Figure 12. 64-Pin Thin Plastic Quad Flat Pack ( 1.4 mm) A64SA 16.00±0.25 SQ 14.00±0. SEATING PLANE 1.60 MAX. 0.10 0.20 MAX Document #: 38-10001 Rev. *F NOTE: 1. ...

Page 14

Package Diagrams (continued 0.793[20.142] 0.817[20.751] 0.101[2.565] 0.111[2.819] 0.050[1.270] BSC. 0.014[0.355] 0.020[0.508] Document #: 38-10001 Rev. *F Figure 13. 32-Pin (450-Mil) SOIC S32.45 1 DIMENSIONS IN INCHES[MM] PACKAGE WEIGHT 1.42gms 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] 32 0.006[0.152] 0.012[0.304] 0.118[2.997] MAX. ...

Page 15

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

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