EWIXP465BAD Intel, EWIXP465BAD Datasheet - Page 28
EWIXP465BAD
Manufacturer Part Number
EWIXP465BAD
Description
Manufacturer
Intel
Datasheet
1.EWIXP465BAD.pdf
(163 pages)
Specifications of EWIXP465BAD
Core Operating Frequency
533MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EWIXP465BAD
Manufacturer:
INTEL
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1 368
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Part Number:
EWIXP465BADT
Manufacturer:
XILINX
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Functional Overview
3.1.10
3.1.11
3.1.12
May 2005
28
Byte-wide parity is an optional configuration of this interface in all modes of operation except:
At the de-assertion of reset, the 25-bit address bus is used to capture configuration information
from the levels that are applied to the pins at this time. External pull-up/pull-down resistors are
used to tie the signals to particular logic levels. (For additional details, see
on page
the IXP45X/IXP46X network processors contain internal weak pull-ups. Depending upon the
system design, pull-down resistors may be the only thing required.
High-Speed, Serial Interfaces
The high-speed, serial interfaces (HSS) are six-signal interfaces that support serial transfer speeds
from 512 KHz to 8.192 MHz, for some models of the IXP45X/IXP46X network processors. (For
processor-specific speeds, see
Each interface allows direct connection of up to four T1/E1 framers and CODEC/SLICs to the
IXP45X/IXP46X network processors. The high-speed, serial interfaces are capable of supporting
various protocols, based on the implementation of the code developed for the network processor
engine core.
For a list of supported protocols, see the Intel
UARTs
The UART interfaces are a 16550-compliant UART with the exception of transmit and receive
buffers. Transmit and receive buffers are 64 bytes-deep versus the 16 bytes required by the
16550 UART specification.
The interfaces can be configured to support speeds from 1,200 Baud to 921 Kbaud. The interfaces
support configurations of:
The request-to-send (RTS_N) and clear-to-send (CTS_N) modem control signals also are available
with the interface for hardware flow control.
GPIO
There are 16 GPIO pins supported by the IXP45X/IXP46X network processors. GPIO pins 0
through 13 can be configured to be general-purpose input or general-purpose output. Additionally,
GPIO pins 0 through 12 can be configured to be an interrupt input.
GPIO Pin 14 can be configured similar to GPIO Pin 13 or as a clock output. The output-clock
configuration can be set at various speeds, up to 33 MHz, with various duty cycles. GPIO Pin 14 is
configured as an input, upon reset.
•
•
•
•
•
Intel StrataFlash
HPI mode
Five, six, seven, or eight data-bit transfers
One or two stop bits
Even, odd, or no parity
40.) If a signal is required to be placed into a pull-up state during this initialization period,
®
K3 synchronous-burst mode
Intel
Table 3 on page
®
IXP45X and Intel
®
19.)
IXP400 Software Programmer’s Guide.
®
IXP46X Product Line of Network Processors Datasheet
Document Number:
“Package Information”
306261-002