GWIXP425ABCT Intel, GWIXP425ABCT Datasheet - Page 26
GWIXP425ABCT
Manufacturer Part Number
GWIXP425ABCT
Description
Manufacturer
Intel
Datasheet
1.GWIXP425ABCT.pdf
(128 pages)
Specifications of GWIXP425ABCT
Core Operating Frequency
400MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Not Compliant
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2.2.2
2.2.3
Intel
Datasheet
26
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
The MAC pipe has six to nine stages:
The MAC pipe supports a data-dependent early terminate where stages MAC 2, MAC 3,
and/or MAC 4 are bypassed.
Deep pipes promote high instruction execution rates only when a means exists to
successfully predict the outcome of branch instructions. The branch target buffer
provides such a means.
Branch Target Buffer (BTB)
Each entry of the 128-entry BTB contains the address of a branch instruction, the
target address associated with the branch instruction, and a previous history of the
branch being taken or not taken. The history is recorded as one of four states:
The BTB can be enabled or disabled via Coprocessor 15, Register 1.
When the address of the branch instruction hits in the BTB and its history is strongly or
weakly taken, the instruction at the branch target address is fetched. When its history
is strongly or weakly not-taken, the next sequential instruction is fetched. In either
case the history is updated.
Data associated with a branch instruction enters the BTB the first time the branch is
taken. This data enters the BTB in a slot with a history of strongly not-taken
(overwriting previous data when present).
Successfully predicted branches avoid any branch-latency penalties in the super
pipeline. Unsuccessfully predicted branches result in a four to five cycle branch-latency
penalty in the super pipeline.
Instruction Memory Management Unit (IMMU)
For instruction pre-fetches, the IMMU controls logical-to-physical address translation,
memory access permissions, memory-domain identifications, and attributes (governing
operation of the instruction cache). The IMMU contains a 32-entry, fully associative
instruction-translation, look-aside buffer (ITLB) that has a round-robin replacement
policy. ITLB entries zero through 30 can be locked.
• The first five stages of the Integer pipe (BTB/Fetch 1 through ALU Execute)
• Data Cache 1
• Data Cache 2
• Data Cache Writeback
• The first four stages of the Integer pipe (BTB/Fetch 1 through Register File/ Shift)
• MAC 1
• MAC 2
• MAC 3
• MAC 4
• Data Cache Writeback
• Strongly
. . . then finish with the following memory stages:
. . . then finish with the following MAC stages:
taken
Intel
• Weakly taken
®
IXP42X product line and IXC1100 control plane processors—Datasheet
• Weakly not taken
Document Number:
• Strongly not
taken
252479-007US
June 2007
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