AD9779ABSVZ Analog Devices Inc, AD9779ABSVZ Datasheet - Page 35

• Manufacturer Part Number: AD9779ABSVZ
• Description: IC DAC 16BIT 1.0GSPS 100TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9779ABSVZ

• Data Interface: Serial
• Design Resources: Interfacing ADL5370 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0016) Interfacing ADL5371 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0017) Interfacing ADL5372 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0018) Interfacing ADL5373 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0019) Interfacing ADL5374 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0020) Interfacing ADL5375 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0021)
• Number Of Bits: 16
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 300mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Resolution (bits): 16bit
• Sampling Rate: 1GSPS
• Input Channel Type: Parallel
• Digital Ic Case Style: QFP
• No. Of Pins: 100
• Operating Temperature Range: -40°C To +85°C
• Number Of Channels: 2
• Resolution: 16b
• Interface Type: Parallel
• Single Supply Voltage (typ): 3.3V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: Interpolation Filter
• Power Supply Requirement: Analog and Digital
• Output Type: Current
• Single Supply Voltage (min): 3.13V
• Single Supply Voltage (max): 3.47V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9779A-EBZ - BOARD EVALUATION FOR AD9779A
• Settling Time: -
• Lead Free Status / Rohs Status: Compliant

INTERPOLATION FILTER BANDWIDTH LIMITS
The AD9776A/AD9778A/AD9779A use a novel interpolation
filter architecture that allows DAC IF frequencies to be gener-
ated anywhere in the spectrum. Figure 68 shows the traditional
choice of DAC IF output bandwidth placement. Note that there
are no possible filter modes in which the carrier can be placed
near 0.5 × f
The filter architecture not only allows the interpolation filter
pass bands to be centered in the middle of the input Nyquist
zones (as explained in this section), but also allows the possi-
bility of a 3 × f
combinations, a carrier of given bandwidth can be placed
anywhere in the spectrum and fall into a possible pass band
of the interpolation filters. The possible bandwidths accessible
with the filter architecture are shown in Figure 69 and Figure 70.
Note that the shifted and nonshifted filter modes are all
accessible by programming the filter mode for the particular
interpolation rate.
Figure 69. Nonshifted Bandwidths Accessible with the Filter Architecture
Figure 68. Traditional Bandwidth Options for TxDAC Output IF
–10
–20
–30
–40
–50
–60
–70
–80
–10
–20
–30
–40
–50
–60
–70
–80
10
10
0
0
–4
–4
DATA
DAC
, 1.5 × f
–3
–3
/8 modulation mode. With all of these filter
–2
–2
ASSUMING 8× INTERPOLATION
ASSUMING 8× INTERPOLATION
DATA
f
f
OUT
OUT
, 2.5 × f
–1
–1
(× Input Data Rate),
(× Input Data Rate),
0
0
DATA
, and so on.
1
1
2
2
3
3
4
4
Rev. A | Page 35 of 60
With this filter architecture, a signal placed anywhere in the
spectrum is possible. However, the signal bandwidth is limited
by the input sample rate of the DAC and the specific placement
of the carrier in the spectrum. The bandwidth restriction resulting
from the combination of filter response and input sample rate is
often referred to as the synthesis bandwidth, because this is the
largest bandwidth that the DAC can synthesize.
The maximum bandwidth condition exists if the carrier is
placed directly in the center of one of the filter pass bands. In
this case, the total 0.1 dB bandwidth of the interpolation filters
is equal to 0.8 × f
width as a fraction of the DAC output sample rate drops by a
factor of 2 for every doubling of interpolation rate. The mini-
mum bandwidth condition exists, for example, if a carrier is
placed at 0.25 × f
response is enabled, the high end of the filter response cuts off
at 0.4 × f
If the shifted filter response is enabled instead, then the low end
of the filter response cuts off at 0.1 × f
end of the signal bandwidth. The minimum bandwidth speci-
fication that applies for a carrier at 0.25 × f
f
spectrum for carriers placed at (±n ± 0.25) × f
any integer.
DATA
Figure 70. Shifted Bandwidths Accessible with the Filter Architecture
. The minimum bandwidth behavior is repeated over the
–10
–20
–30
–40
–50
–60
–70
–80
10
0
DATA
–4
, thus limiting the high end of the signal bandwidth.
–3
DATA
DATA
AD9776A/AD9778A/AD9779A
. As Table 19 shows, the synthesis band-
. In this situation, if the nonshifted filter
–2
ASSUMING 8× INTERPOLATION
f
OUT
–1
(× Input Data Rate),
0
DATA
1
, thus limiting the low
DATA
2
DATA
is therefore 0.3 ×
, where n is
3
4