AD9779ABSVZ Analog Devices Inc, AD9779ABSVZ Datasheet - Page 42

• Manufacturer Part Number: AD9779ABSVZ
• Description: IC DAC 16BIT 1.0GSPS 100TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9779ABSVZ

• Data Interface: Serial
• Design Resources: Interfacing ADL5370 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0016) Interfacing ADL5371 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0017) Interfacing ADL5372 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0018) Interfacing ADL5373 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0019) Interfacing ADL5374 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0020) Interfacing ADL5375 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0021)
• Number Of Bits: 16
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 300mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Resolution (bits): 16bit
• Sampling Rate: 1GSPS
• Input Channel Type: Parallel
• Digital Ic Case Style: QFP
• No. Of Pins: 100
• Operating Temperature Range: -40°C To +85°C
• Number Of Channels: 2
• Resolution: 16b
• Interface Type: Parallel
• Single Supply Voltage (typ): 3.3V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: Interpolation Filter
• Power Supply Requirement: Analog and Digital
• Output Type: Current
• Single Supply Voltage (min): 3.13V
• Single Supply Voltage (max): 3.47V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9779A-EBZ - BOARD EVALUATION FOR AD9779A
• Settling Time: -
• Lead Free Status / Rohs Status: Compliant

AD9776A/AD9778A/AD9779A
INPUT DATA PORTS
The AD9776A/AD9778A/AD9779A can operate in two data
input modes: dual port mode and single port mode. For the
default dual port mode (Single Port = 0), each DAC receives
data from a dedicated input port. In single port mode (Single
Port = 1), both DACs receive data from Port 1. In single port
mode, DAC1 and DAC2 data is interleaved and the TXENABLE
input is used to steer data to the intended DAC. In dual port
mode, the TXENABLE input is used to power down the digital
data path.
In dual port mode, the data must be delivered at the input data
rate. In single port mode, data must be delivered at twice the
input data rate of each DAC. Because the data inputs function
up to a maximum of 300 MSPS, it is only practical to operate
with input data rates up to 150 MHz per DAC in single port mode.
In dual port and single port modes, a data clock output
(DATACLK) signal is available as a fixed time base with which
to drive data from an FPGA or other data source. This output
signal operates at the input data rate.
SINGLE PORT MODE
In single port mode, data for both DACs is received on the Port 1
input bus (P1D<15:0>). I and Q data samples are interleaved
and are sampled on the rising edges of DATACLK. Along with
the data, a framing signal must be supplied on the TXENABLE
input (Pin 39), which steers incoming data to its respective DAC.
When TXENABLE is high, the corresponding data-word is sent
to the I DAC and when TXENABLE is low the corresponding data
is sent to the Q DAC. The timing of the digital interface in
interleaved mode is shown in Figure 83.
The Q First bit (Register 0x02, Bit 0) controls the pairing order
of the input data. With the Q First bit set to the default of 0, the
IQ pairing sent to the DACs is the two input data-words corres-
ponding to TXENABLE low followed by TXENABLE high. With
the Q First bit set to 1, the IQ pairing sent to the DACs is the
two input data-words corresponding to TXENABLE high followed
by TXENABLE low. Note that with either order pairing, the
data sent with TXENABLE high is directed to the I DAC, and
the data sent with TXENABLE low is directed to the Q DAC.
Q FIRST = 0
Q FIRST = 1
Q DAC<15:0>
Q DAC<15:0>
I DAC<15:0>
I DAC<15:0>
P1D<15:0>
IQSELECT
DATACLK
Figure 83. Single Port Mode Digital Interface Timing
P1D<1>
Rev. A | Page 42 of 60
P1D<2>
P1D<3>
P1D<4>
P1D<1>
P1D<2>
P1D<1>
P1D<0>
DUAL PORT MODE
In dual port mode, data for each DAC is received on the
respective input bus (P1D<15:0> or P2D<15:0>). I and Q data
arrive simultaneously and are sampled on the rising edge of the
DATACLK signal. The TXENABLE signal must be high to enable
the transmit path.
INPUT DATA REFERENCED TO DATACLK
The simplest method of interfacing to the AD9776A/AD9778A/
AD9779A is when the input data is referenced to the DATACLK
output. The DATACLK output is a buffered version (with some
fixed delay) of the internal clock that is used to latch the input
data. Therefore, if setup and hold times of the input data with
respect to DATACLK are met, the input data is latched correctly.
Detailed timing diagrams for the single and dual port cases
using DATACLK as the timing reference are shown in Figure 82.
Table 25 shows the setup and hold time requirements for the
input data over the operating temperature range of the device.
Also shown is the keep out window (KOW). The keep out
window is the sum of the setup and hold times of the interface.
This is the minimum amount of time valid data must be
presented to the device in order to ensure proper sampling.
DATACLK Frequency Settings
The DATACLK signal is derived from the internal DAC sample
clock, DACCLK. The frequency of the DATACLK output depends
on several programmable settings. Normally, the frequency of
DATACLK is equal to the input data rate. The relationship
between the frequency of DACCLK and DATACLK is
The variables IF, ZS, SP, and DATACLKDIV have the values
shown in Table 24.
DATACLK
DATA
P1D<5>
Figure 82. Input Data Port Timing, Data Referenced to DATACLK
f
DATACLK
P1D<6>
P1D<3>
P1D<4>
P1D<3>
P1D<2>
=
P1D<7>
IF
×
ZS
P1D<8>
P1D<5>
P1D<6>
P1D<5>
P1D<4>
×
SP
t
SDATACLK
f
DACCLK
×
DATACLKDIV
t
HDATACLK